Abstract: A method and apparatus utilizing a single processor and a plurality of memories for providing audio synchronization including writing an incoming PES audio stream having header information, PTS timing information and payload information and audio information to an input buffer. The method and apparatus further includes reading the incoming audio stream from the input buffer and parsing the timing information and the audio information. The audio information, ES information, is written to an intermediate buffer. Based on the timing information, the method and apparatus further includes reading the audio information from the intermediate buffer and decoding the audio information to generate decoded audio information, PCM information. The method and apparatus includes writing the decoded audio information in an output buffer, wherein the decoded audio information may be provided from the output buffer to a digital-to-analog converter and thereupon provided to an audio system.

Abstract: Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.

Abstract: A method and apparatus utilizing a single processor and a plurality of memories for providing audio synchronization including writing an incoming PES audio stream having header information, PTS timing information and payload information and audio information to an input buffer. The method and apparatus further includes reading the incoming audio stream from the input buffer and parsing the timing information and the audio information. The audio information, ES information, is written to an intermediate buffer. Based on the timing information, the method and apparatus further includes reading the audio information from the intermediate buffer and decoding the audio information to generate decoded audio information, PCM information. The method and apparatus includes writing the decoded audio information in an output buffer, wherein the decoded audio information may be provided from the output buffer to a digital-to-analog converter and thereupon provided to an audio system.

Abstract: A method and apparatus utilizing a single processor and a plurality of memories for providing audio synchronization including writing an incoming PES audio stream having header information, PTS timing information and payload information and audio information to an input buffer. The method and apparatus further includes reading the incoming audio stream from the input buffer and parsing the timing information and the audio information. The audio information, ES information, is written to an intermediate buffer. Based on the timing information, the method and apparatus further includes reading the audio information from the intermediate buffer and decoding the audio information to generate decoded audio information, PCM information. The method and apparatus includes writing the decoded audio information in an output buffer, wherein the decoded audio information may be provided from the output buffer to a digital-to-analog converter and thereupon provided to an audio system.

Abstract: Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.

Abstract: A display data format conversion circuit and method facilitates display of data on a plurality of display devices based on display data of a source display device. The system incorporates a resynchronization circuit that dynamically varies a frame rate of one display device based on the instantaneous frame rate of the source device to maintain synchronization of the displays. A display timing generator circuit for a first display, such as an LCD display, produces a first display timing signal. The resynchronization circuit is operatively responsive to the first display timing signal and a second display timing signal wherein the second display timing signal is associated with a second display device, such as a source display device. In one embodiment, the resynchronization circuit includes a vertical blanking time variation circuit that adaptively and continuously varies the frame rate of the first display device by varying a vertical blanking time of the first display device.