Abstract: Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.

Abstract: Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.

Abstract: A method of fabricating an integrated circuit (IC) chip. A standard cell macro (e.g., an Off Chip Interface (OCI) cell) is defined with circuit elements identified as in a macro domain. A variable macro boundary is defined for the standard cell macro. Shapes are selectively added to design layers in the macro boundary to occupy existing white space. Each supplemented layer is checked for technology rules violations in the macro boundary. Each layer is also checked for known sensitivities in the macro boundary.

Abstract: An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated, or a combination of rotated and non-rotated IO cells may form the IO collar. For each edge of the IC chip having rotated IO cells, each edge may have the same number of stacks of IO cells or a different number of stacks of IO cells.

Abstract: Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.