Patents by Inventor Wai Ling Lee
Wai Ling Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230361003Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: June 29, 2023Publication date: November 9, 2023Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Publication number: 20230253295Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: April 10, 2023Publication date: August 10, 2023Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Patent number: 11652026Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: January 28, 2022Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Publication number: 20230092309Abstract: The invention provides nanoemulsion for preparing plant-based meat, the nanoemulsion has a particle size ranging from 300 nm to 320 nm. The plant-based meat prepared by using the nanoemulsion of the present invention can retain flavors after various cooking methods. The plant-based meat of the present invention can withstand different pH values and temperatures, and remains stable at different concentrations of salt, sugar, lipids, protein, carbohydrates and a variety of organic compounds, and will not lower consumer’s flavor expectations and perceptions. The plant-based meat of the present invention retains more flavors, so less flavoring is needed, and the cost will be reduced.Type: ApplicationFiled: November 11, 2021Publication date: March 23, 2023Inventors: Chui Chui CHEUNG, Mabel Wai Ling LEE, Cheuk Ying WONG
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Patent number: 11398415Abstract: Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.Type: GrantFiled: June 25, 2019Date of Patent: July 26, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Patent number: 11393741Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: January 22, 2021Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Patent number: 11393758Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.Type: GrantFiled: June 25, 2019Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
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Publication number: 20220157694Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Publication number: 20210320051Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: January 22, 2021Publication date: October 14, 2021Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Patent number: 10903142Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: May 3, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Publication number: 20200091040Abstract: Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.Type: ApplicationFiled: June 25, 2019Publication date: March 19, 2020Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Publication number: 20200083170Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.Type: ApplicationFiled: June 25, 2019Publication date: March 12, 2020Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
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Publication number: 20200043831Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: May 3, 2019Publication date: February 6, 2020Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Patent number: 9978735Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.Type: GrantFiled: September 28, 2016Date of Patent: May 22, 2018Assignee: Altera CorporationInventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
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Publication number: 20180090474Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
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Patent number: 9842181Abstract: The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.Type: GrantFiled: May 24, 2016Date of Patent: December 12, 2017Assignee: Altera CorporationInventors: Kyung Suk Oh, Yee Huan Yew, Chee Cheong Tan, Mei See Chin, Wai Ling Lee, Loke Yip Foo, Chooi Ian Loh, Hui Lee Teng
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Patent number: 6442634Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.Type: GrantFiled: May 18, 2001Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Wai Ling Lee, Vincent P. Zeyak, Jr.
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Publication number: 20010027502Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.Type: ApplicationFiled: May 18, 2001Publication date: October 4, 2001Inventors: Timothy C. Bronson, Wai Ling Lee, Vincent P. Zeyak
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Patent number: 6279064Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.Type: GrantFiled: April 29, 2000Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Wai Ling Lee, Vincent P. Zeyak, Jr.
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Patent number: 6065088Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.Type: GrantFiled: August 31, 1998Date of Patent: May 16, 2000Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Wai Ling Lee, Vincent P. Zeyak, Jr.