Patents by Inventor Wai Loon Ho

Wai Loon Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8954907
    Abstract: Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: February 10, 2015
    Assignee: Altera Corporation
    Inventors: Syamsul Hani Hasran, Ian Eu Meng Chan, Wai Loon Ho, Lee Shyuan Heng, Min Meng Loo, Mohd Yusuf Abdul Hamid
  • Patent number: 8423932
    Abstract: Techniques for generating an emulated logic block are provided. The techniques include identifying a logic block in one integrated circuit (IC) design that needs to be emulated in another IC design. The logic block may be a physical logic block on the IC design and a non-existent logic block on the other IC design. Logic elements are used to form an emulated logic block that shares substantially the same functionality as the actual logic block. The logic elements are connected to perform logic functions associated with the actual logic block and are grouped together to form an emulated logic block based on the actual logic block.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: April 16, 2013
    Assignee: Altera Corporation
    Inventors: Syamsul Hani Hasran, Ian Eu Meng Chan, Wai Loon Ho, Lee Shyuan Heng, Min Meng Loo, Mohd Yusuf Abdul Hamid
  • Patent number: 8181146
    Abstract: A method for performing equivalency checking between circuit designs is provided. The method includes partitioning the circuit designs into logic cones. The method includes comparing corresponding logic cones for equivalency. The comparing includes identifying constant registers feeding nonequivalent logic cones, and propagating a constant value associated with the constant register. The method includes repeating the comparing with the propagated constant values inserted in one of the corresponding logic cones. The method also includes detecting duplicate registers feeding nonequivalent logic cones in embodiments where no constant registers feeding nonequivalent logic cones are found.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: May 15, 2012
    Assignee: Altera Corporation
    Inventors: Yau Loong Low, Wai Loon Ho