Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract: A method for fabricating a magnetic recording transducer is described. The magnetic recording transducer has an underlayer and at least one layer on the underlayer. The layer(s) are capable of including an aperture that exposes a portion of the underlayer. The method includes providing a neutralized aqueous solution having a chemical buffer therein. The chemical buffer forms a nonionic full film corrosion inhibitor. The method also includes exposing a portion of the magnetic recording transducer including the layer(s) to the neutralized aqueous solution including the chemical buffer. In one aspect this exposure occurs through a chemical mechanical planarization.

Abstract: A method for fabricating a magnetic recording transducer is described. The magnetic recording transducer has an underlayer and at least one layer on the underlayer. The layer(s) are capable of including an aperture that exposes a portion of the underlayer. The method includes providing a neutralized aqueous solution having a chemical buffer therein. The chemical buffer forms a nonionic full film corrosion inhibitor. The method also includes exposing a portion of the magnetic recording transducer including the layer(s) to the neutralized aqueous solution including the chemical buffer. In one aspect this exposure occurs through a chemical mechanical planarization.

Abstract: A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.

Abstract: A cladding structure for a conductive line used to switch a free layer in a MTJ is disclosed and includes two cladding sidewalls on two sides of the conductive line, a top cladding portion on a side of the conductive line facing away from the MTJ, and a highly conductive, non-magnetic spacing control layer formed between the MTJ and conductive line. The spacing control layer has a thickness of 0.02 to 0.12 microns to maintain the distance separating free layer and conductive line between 0.03 and 0.15 microns. The spacing control layer is aligned parallel to the conductive line and contacts a plurality of MTJ elements in a row of MRAM cells. Half-select error problems are avoided while maintaining high write efficiency. A spacing control layer may be formed between a word line and a bottom electrode in a top pinned layer or dual pinned layer configuration.

Abstract: A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.

Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract: A cladding structure for a conductive line used to switch a free layer in a MTJ is disclosed and includes two cladding sidewalls on two sides of the conductive line, a top cladding portion on a side of the conductive line facing away from the MTJ, and a highly conductive, non-magnetic spacing control layer formed between the MTJ and conductive line. The spacing control layer has a thickness of 0.02 to 0.12 microns to maintain the distance separating free layer and conductive line between 0.03 and 0.15 microns. The spacing control layer is aligned parallel to the conductive line and contacts a plurality of MTJ elements in a row of MRAM cells. Half-select error problems are avoided while maintaining high write efficiency. A spacing control layer may be formed between a word line and a bottom electrode in a top pinned layer or dual pinned layer configuration.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a layer of ruthenium near the silicon nitride surface. The ruthenium is a good electrical conductor and it responds differently from Ta and TaN to certain etchants. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. Thus, said included layer of ruthenium may be used as an etch stop layer during the etching of Ta and/or TaN while the latter materials may be used to form a hard mask for etching the ruthenium without significant corrosion of the silicon nitride surface.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a layer of ruthenium near the silicon nitride surface. The ruthenium is a good electrical conductor and it responds differently from Ta and TaN to certain etchants. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. Thus, said included layer of ruthenium may be used as an etch stop layer during the etching of Ta and/or TaN while the latter materials may be used to form a hard mask for etching the ruthenium without significant corrosion of the silicon nitride surface.