Abstract: Embodiments of information handling systems and methods are provided herein to selectively control ownership of a hardware watchdog timer (WDT) provided on a system platform of an information handling system (IHS), which is configured to store and execute boot firmware, an operating system (OS) and one or more user applications. One embodiment of a method disclosed herein may include receiving user input in a boot setup utility of the boot firmware to select between OS-ownership and user application-ownership of the hardware WDT during OS runtime, and controlling ownership of the hardware WDT during OS runtime based on the user input received in the boot setup utility. Another embodiment of a method disclosed herein may authorize one or more user applications prior to controlling ownership of the hardware WDT during OS runtime, so that only authorized user applications are enabled to use the hardware WDT.

Abstract: Embodiments of information handling systems and methods are provided herein to selectively control ownership of a hardware watchdog timer (WDT) provided on a system platform of an information handling system (IHS), which is configured to store and execute boot firmware, an operating system (OS) and one or more user applications. One embodiment of a method disclosed herein may include receiving user input in a boot setup utility of the boot firmware to select between OS-ownership and user application-ownership of the hardware WDT during OS runtime, and controlling ownership of the hardware WDT during OS runtime based on the user input received in the boot setup utility. Another embodiment of a method disclosed herein may authorize one or more user applications prior to controlling ownership of the hardware WDT during OS runtime, so that only authorized user applications are enabled to use the hardware WDT.

Abstract: A computer system and a method for allocating power to hot-plugged adapter cards placed in a card slot so as to delay, the power allocation until a user is clear of the adapter card. The computer system conventionally includes a processor, a card slot in data communication with the processor, a memory in data communication with the processor, and a power supply in electrical communication with the processor. The memory stores computer-readable data that includes code to be operated on by the processor to allocate power to the card slot upon both a detection of a change of state of the card slot and the occurrence of a predefined system event. The predefined system event is typically a system interrupt that is generated in response to an activation of a switch in electrical communication with the processor.

Abstract: A dual processor computer system is disclosed that includes a processor failure detection and recovery circuit which initially designates one of the processing units as the lead-off master and the other processing unit as a slave. The processor failure detection and recovery circuit includes a timer unit which begins the countdown of a predetermined period in response to the initial resetting of the master and slave processors. The processor failure and detection circuit further includes a control unit which determines whether the master processor fails to reset or suffers from a hard failure by determining whether a bit of a storage unit has been set in response to software code intended for execution by the master processor during initialization. If the bit is not set before the lapse of the predetermined time period following reset, the control unit changes the designation of the slave processor to master and simultaneously resets the re-designated master.

Abstract: A computer which carries its BIOS in a Flash EPROM. A UV-EPROM carries a redundant BIOS, which can be overlaid onto the BIOS address space by selection with a physical switch.The BIOS contains a small core software program, at the BIOS entry point, which checks BIOS integrity, and provides for reloading the Flash EPROM's BIOS if needed (from a floppy disk, or by copying the entire contents of the UV-EPROM).