Abstract: Power management may be performed in a basic input/output system (BIOS) of an information handling system to provide flexibility in system operation. The BIOS may include a user setting specifying a power level, and that power level used to control a central processing unit (CPU) or other hardware components. For example, the BIOS power level may specify a sustained power setting for the CPU. One example sustained power setting is the PL1 value, which is a fixed value that specifies a thermal design power (TDP) for the CPU. As another example, the power level may specify whether to enable and/or disable a discrete graphics processing unit (GPU) or other hardware component operating from the same battery as the CPU.

Abstract: Power management may be performed in a basic input/output system (BIOS) of an information handling system to provide flexibility in system operation. The BIOS may include a user setting specifying a power level, and that power level used to control a central processing unit (CPU) or other hardware components. For example, the BIOS power level may specify a sustained power setting for the CPU. One example sustained power setting is the PL1 value, which is a fixed value that specifies a thermal design power (TDP) for the CPU. As another example, the power level may specify whether to enable and/or disable a discrete graphics processing unit (GPU) or other hardware component operating from the same battery as the CPU.

Abstract: Systems and methods for establishing Core Root of Trust Measurement (CRTM) for Basic Input/Output (BIOS) image recovery are described. In some embodiments, an Information Handling System (IHS) may include a processor and a BIOS coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to: during a boot process, verify integrity of a BIOS recovery image using a CRTM, and determine whether to restore the BIOS recovery image in response to the verification.

Abstract: An information handling system includes an application installer, a gateway service, and a driver update service. The application installer retrieves an application from an online application store, and installs the application. The gateway service receives a request to enable a hardware identifier from the application, and enables the hardware identifier and trigger a driver update service. The driver update service checks for an updated driver for the hardware identifier, and downloads and installs the updated driver.

Abstract: Systems and methods for establishing Core Root of Trust Measurement (CRTM) for Basic Input/Output (BIOS) image recovery are described. In some embodiments, an Information Handling System (IHS) may include a processor and a BIOS coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to: during a boot process, verify integrity of a BIOS recovery image using a CRTM, and determine whether to restore the BIOS recovery image in response to the verification.

Abstract: A method includes detecting a storage device that has a boot file and a relative path name that corresponds to the boot file, determining a hardware path name corresponding to the storage device, obtaining from the storage device the relative path name, combining the hardware path name and the relative path name to generate a full path name to the boot file, and storing the full path name within a persistent memory.

Abstract: A method includes detecting a storage device that has a boot file and a relative path name that corresponds to the boot file, determining a hardware path name corresponding to the storage device, obtaining from the storage device the relative path name, combining the hardware path name and the relative path name to generate a full path name to the boot file, and storing the full path name within a persistent memory.

Abstract: An information handling system and a method of using it can allow the information handling system to be started or restarted and have an operating system loaded, even if a boot variable within a persistent memory is currently invalid. The method can detect and determine a hardware path name to a new drive that has an operating system. The new drive can have a relative path name to boot entries that include a pointer to a boot file. The boot file can be executed to run a boot loader that loads the operating system. During loading of the operating system, other boot entries within the drive can provide boot parameters. The boot variable within persistent memory, and potentially the relative path name or boot parameter(s) can be updated on the new drive. In a particular embodiment, the information handling system can include a unified extensible firmware interface (UEFI).

Abstract: An information handling system and a method of using it can allow the information handling system to be started or restarted and have an operating system loaded, even if a boot variable within a persistent memory is currently invalid. The method can detect and determine a hardware path name to a new drive that has an operating system. The new drive can have a relative path name to boot entries that include a pointer to a boot file. The boot file can be executed to run a boot loader that loads the operating system. During loading of the operating system, other boot entries within the drive can provide boot parameters. The boot variable within persistent memory, and potentially the relative path name or boot parameter(s) can be updated on the new drive. In a particular embodiment, the information handling system can include a unified extensible firmware interface (UEFI).

Abstract: An information handling system includes a processor and a system memory coupled to the processor. The system has a plurality of persistent mass storage devices including first and second storage devices. A device controller includes a first port operably connected to the first storage device and a second port operably connected to the second storage device. The controller transfers data between system memory and the storage devices. System firmware includes instructions to configure the controller to define a first command list and frame information structure (FIS) associated with the first port and a second command list and FIS associated with the second port where the first and second command lists share a common block of system memory.

Abstract: An information handling system includes a processor and a system memory coupled to the processor. The system has a plurality of persistent mass storage devices including first and second storage devices. A device controller includes a first port operably connected to the first storage device and a second port operably connected to the second storage device. The controller transfers data between system memory and the storage devices. System firmware includes instructions to configure the controller to define a first command list and frame information structure (FIS) associated with the first port and a second command list and FIS associated with the second port where the first and second command lists share a common block of system memory.

Abstract: A method and system for booting a computer system is provided in which the boot order of the computer system is displayed to the user in a manner such that the name of each bootable device and the location of each bootable device in the architecture of the computer system are displayed to the user upon entering a setup routine. The boot order displayed may also identify other information about the bootable devices of the computer system, including the operating and maximum speed of the devices and whether the devices are embedded devices. The boot order may be changed by the user by entering setup and manipulating the displayed list of bootable devices.

Abstract: A method and system for displaying information at a remote display device from an information processing system that lacks video display components causes the information processing system to initiate system memory to store video information despite the lack of video components, thus allowing applications to write display information to the system memory and allowing the information handling system to re-direct the display information to the remote display. For instance, the information handling system BIOS includes a video function module that detects a lack of video display components, determines that the information handling system is a headless server, and initiates system memory to store video information. A remote display module associated with the BIOS monitors the system memory and re-directs detected display information stored in the system memory to a remote information handling system that displays the information.

Abstract: A method for handling system management interrupts in multiprocessors systems is provided. After the processors of the system enter system management mode, one of the processors of the system is designated to handle the system management interrupt. The processor designated to handle the system management interrupt scans a memory location that includes a memory space associated with the saved contents of the processor registers of each processor. After locating a SMI signature in one of the memory spaces associated with the respective processors of the system, the SMI handler of the processor designated to handle the system management interrupts, retrieves any necessary parameters for the system management interrupt from the memory space associated with the SMI signature, thereby allowing a processor to cause the issuance a SMI, to pass a set of parameters for the software SMI, and to permit a second processor to receive the parameters and handle the software SMI.

Abstract: A system for enabling remote console redirection on a computer system having a remote monitor connector circuit located on a different computer bus than a local monitor connector circuit. In one example, a remote monitor connector circuit located on a PCI computer bus generates system management interrupts (SMIs) via an interrupt controller to a system processor of a computer system such as a server. In response to a SMI, the system processor invokes an interrupt handler to determine the source of the interrupt. In response to determining that the SMI was generated by the remote monitor connector circuit, the system processor places the video data being provided to a local monitor connector circuit (such as a graphics accelerator conforming to the Accelerated Graphics Port interface standard) into a shared memory location accessible by both the system processor and the remote monitor connector circuit. The remote monitor connector circuit provides the video data to a remote monitor via e.g.

Abstract: A system and method for disabling and re-enabling peripheral devices (PDs) in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a host-bus-to-peripheral-device-bus (HB/PDB) bridge coupled to the host bus, at least one PD, at least one peripheral device bus coupling the HB/PDB bridge and at least one PD, and a device, typically in the form of a digital gate, for selectively disabling and re-enabling at least one PD. The disclosed method operates in connection with a computer system having a CPU, a HB/PDB bridge coupled to the CPU and capable of sending a device-configuration-space-access-signal (DCSAS) to the DCSAS input pin of a target PD when attempting an access operation, such as a read or a write operation, on the target PD, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PD.

Abstract: A system and method for disabling and re-enabling PCI-compliant devices in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a PCI/Host bridge coupled to the host bus, one or more PCI-compliant devices, a PCI bus coupling the PCI/Host bridge and the PCI-compliant devices, and a device, typically in the form of a digital gate, for selectively disabling or re-enabling one or more of the PCI-compliant devices. The disclosed method operates in connection with a computer system having a CPU, a PCI/Host bridge coupled to the CPU and capable of sending an IDSEL signal to the IDSEL input pin of a target PCI-compliant device when attempting a read or write operation on the target PCI-compliant device, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PCI-compliant device.