Abstract: An electrostatic discharge protection device for protecting the input of a circuit comprises a p-channel MOSFET (P-FET). The n-well with P+ implants of the P-FET provides a functional lateral PNP bipolar transistor that is coupled between the input of the circuit and a supply node of the circuit. Biasing circuitry controls biasing of the gate and n-well body of the P-FET in accordance with the voltage at the input of the circuit.

Abstract: A resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit is presented for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit or integrated circuit chip. The suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit.