Abstract: In a distributed computing system comprising multiple processor types, a method of provisioning includes receiving a request from a client device for execution of a function. A first data structure identifies implementations of the function and compatible processor types for each implementation. A second data structure identifies available processors in the system. Compatible processor types matching available processors are candidates for execution of the function. A provisioning instruction is created for allocating resources for execution of the function.

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Abstract: Embodiments described herein provide various examples of a joint face-detection and head-pose-angle-estimation system based on using a small-scale hardware CNN module such as the built-in CNN module in HiSilicon Hi3519 system-on-chip. In some embodiments, the disclosed joint face-detection and head-pose-angle-estimation system is configured to jointly perform multiple tasks of detecting most or all faces in a sequence of video frames, generating pose-angle estimations for the detected faces, tracking detected faces of a same person across the sequence of video frames, and generating “best-pose” estimation for the person being tracked. The disclosed joint face-detection and pose-angle-estimation system can be implemented on resource-limited embedded systems such as smart camera systems that are only integrated with one or more small-scale CNN modules.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.

Abstract: A method comprises forming a buried layer over a substrate, forming an epitaxial layer over the buried layer, forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench, depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench, removing the dielectric layer in the second trench and forming a first gate region in the first trench and a second gate region in the second trench.

Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected. The region between the first and the second gate electrodes overlaps the doped semiconductor region.

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

Abstract: A device (1) comprises: a cylindrical shell (4); a first spring (5) encased inside the cylindrical shell (4); a second spring (6) encased inside the cylindrical shell (4); a separator (13) in the cylindrical shell (4) separating the first and second springs (5, 6); a first end plate (12) on a first side (13a) of the separator (13) and a second end plate (11) on a second side (13b) of the separator (13); a first rod (2) and a second rod (3) passing openings (20a, 20b) provided at each end of the cylindrical shell (4), with the first rod (2) connected to the first end plate (12) and the second rod (3) connected to the second end plate (11); and a spacer (14) inserted between the first end plate (12) and the first spring (5).

Abstract: Processor system with a general purpose processor and a cryptographic processor dedicated to performing cryptographic operations and enforcing the security of critical security parameters. The cryptographic processor prevents exposure of critical security parameters outside the cryptographic processor itself, and instead implements a limited scripting engine, which can be used by the general purpose processor to execute operations that require the critical security parameters.

Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

Abstract: Systems, methods, and non-transitory computer-readable media can determine a request for a page of content items to be obtained from a content provider, the request being associated with a cache key. A determination is made that access to the content provider is unavailable. A determination is made that a response corresponding to the page of content items is stored in a local data store based at least in part on the cache key, wherein the response was previously obtained from the content provider. The page of content items is presented through a display screen associated with a computing device.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.

Abstract: A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.

Abstract: Embodiments described herein provide various examples of an age and gender estimation system capable of performing age and gender classifications on face images having sizes greater than the maximum number of input pixels supported by a given small-scale hardware convolutional neutral network (CNN) module. In some embodiments, the proposed age and gender estimation system can first divide a high-resolution input face image into a set of image patches with judiciously designed overlaps among neighbouring patches. Each of the image patches can then be processed with a small-scale CNN module, such as the built-in CNN module in Hi3519 SoC. The outputs corresponding to the set of image patches can be subsequently merged to obtain the output corresponding to the input face image, and the merged output can be further processed by subsequent layers in the age and gender estimation system to generate age and gender classifications for the input face image.

Abstract: Embodiments of a convolutional neutral network (CNN) system based on using resolution-limited small-scale CNN modules are disclosed. In some embodiments, a CNN system includes: a receiving module for receiving an input image of a first image size, the receiving module can be used to partition the input image into a set of subimages of a second image size; a first processing stage that includes a first hardware CNN module configured with a maximum input image size, the first hardware CNN module is configured to sequentially receive the set of subimages and sequentially process the received subimages to generate a set of outputs; a merging module for merging the sets of outputs into a set of merged feature maps; and a second processing stage for receiving the set of feature maps and processing the set of feature maps to generate an output including at least one prediction on the input image.

Abstract: Embodiments described herein provide various examples of a face detection system, based on using a small-scale hardware convolutional neutral network (CNN) module configured into a multi-task cascaded CNN. In some embodiments, a subimage-based CNN system can be configured to be equivalent to a large-scale CNN that processes the entire input image without partitioning such that the output of the subimage-based CNN system can be exactly identical to the output of the large-scale CNN. Based on this observation, some embodiments of this patent disclosure make use of the subimage-based CNN system and technique on one or more stages of a cascaded CNN or a multitask cascaded CNN (MTCNN) so that a larger input image to a given stage of the cascaded CNN or the MTCNN can be partitioned into a set of subimages of a smaller size. As a result, each stage of the cascaded CNN or the MTCNN can use the same small-scale hardware CNN module that is associated with a maximum input image size constraint.

Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.

Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.