Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Abstract: A system for relaying communication for a PHY/data link level communication protocol may include a first device having a first and second transceiver, the first transceiver having a first protocol controller configured to detect a first bus condition and second transceiver having a second protocol controller configured to detect a second bus condition and a switching matrix coupled to the first and second transceiver and configured to operate in a relaying mode to enable: the first protocol controller to control a physical layer of the second transceiver and enables the second protocol controller to control a physical layer of the first transceiver, a physical layer of a first transmitter of the first transceiver to receive an output of a second receiver of the second transceiver, and the physical layer of a second transmitter of the second transceiver to receive an output of a first receiver of the first transceiver.

Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.

Abstract: A multi-path audio amplification system that provides an output drive signal to electromechanical output transducers provides improved undistorted headroom, reduced path switching noise, and/or improved frequency response performance. Multiple signal amplification paths receive an audio input signal and have corresponding multiple output stages that have differing output impedances. A mode selector selects an active one of the multiple signal amplification paths is selected to supply the output drive signal. Outputs of the multiple output stages are coupled to the electromechanical transducer to provide the output drive signal and at least one of the multiple signal amplification paths includes an equalization filter for filtering the audio input signal to compensate for phase or gain differences referenced from the input to the outputs of the multiple output stages due to interaction between the differing output impedances and an impedance of the electromechanical transducer.

Abstract: An amplification system with an output driver stage for providing an output signal to acoustic output transducers such as speakers or haptic output devices removes signal distortion caused by output stage non-linearities by pre-distorting an input signal. The system includes the output driver stage, an input stage for receiving the input signal, and a processing block that receives the input signal and provides an output signal to the output driver stage. The processing block includes a pre-distortion circuit that applies a pre-distortion function to the input signal to generate the output signal if a signal level of the input signal is greater than a threshold amplitude, and if the signal level is less than or equal to the threshold amplitude, generates the output signal from the input signal by bypassing the pre-distortion circuit.

Abstract: A multi-path audio amplification system that provides an output drive signal to electromechanical output transducers provides improved undistorted headroom, reduced path switching noise, and/or improved frequency response performance. Multiple signal amplification paths receive an audio input signal and have corresponding multiple output stages that have differing output impedances. A mode selector selects an active one of the multiple signal amplification paths is selected to supply the output drive signal. Outputs of the multiple output stages are coupled to the electromechanical transducer to provide the output drive signal and at least one of the multiple signal amplification paths includes an equalization filter for filtering the audio input signal to compensate for phase or gain differences referenced from the input to the outputs of the multiple output stages due to interaction between the differing output impedances and an impedance of the electromechanical transducer.

Abstract: An amplification system with an output driver stage for providing an output signal to acoustic output transducers such as speakers or haptic output devices removes signal distortion caused by output stage non-linearities by pre-distorting an input signal. The system includes the output driver stage, an input stage for receiving the input signal, and a processing block that receives the input signal and provides an output signal to the output driver stage. The processing block includes a pre-distortion circuit that applies a pre-distortion function to the input signal to generate the output signal if a signal level of the input signal is greater than a threshold amplitude, and if the signal level is less than or equal to the threshold amplitude, generates the output signal from the input signal by bypassing the pre-distortion circuit.

Abstract: An audio processing system reduces perception of audible artifacts due to changes in an element in an audio channel of the audio processing system. The system reproduces an audio input signal and produces an audio output signal with the audio channel. The channel has an adjustable or selectable element that, responsive to a control signal, changes a characteristic of the audio processing channel, which generates a transient in the audio output signal. The systems include a level detector for measuring a signal level of the audio input signal and a controller responsive to an output of the level detector to determine a masking time interval available from the audio output signal due to signal content in the audio input signal. The controller generates the control signal to change the characteristic of the audio processing channel so that at least a portion of the transient occurs in the masking time interval.

Abstract: A system may include a digital delta-sigma modulator configured to receive a digital audio input signal and quantize the digital audio input signal into a quantized signal, a filter configured to receive the quantized signal and perform filtering on the quantized signal to generate a filtered quantized signal, the filter having a variable group delay, and a current-mode digital-to-analog converter configured to receive the filtered quantized signal and convert the filtered quantized signal into an equivalent current-mode analog audio signal.

Abstract: A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.

Abstract: A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

Abstract: A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

Abstract: A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.

Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

Abstract: A system may include a digital delta-sigma modulator configured to receive a digital audio input signal and quantize the digital audio input signal into a quantized signal, a filter configured to receive the quantized signal and perform filtering on the quantized signal to generate a filtered quantized signal, the filter having a variable group delay, and a current-mode digital-to-analog converter configured to receive the filtered quantized signal and convert the filtered quantized signal into an equivalent current-mode analog audio signal.

Abstract: A delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

Abstract: A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.