Abstract: A memory circuit includes a memory structure having sets of redundant columns where each set of redundant columns can replace a column of the memory array that may include a defective cell. Selection of the redundant columns for a memory access is accomplished by performing an address comparison between the address provided to the memory and one or more predetermined values that indicate which portion of the data array each set of redundant columns replaces. Based on this address comparison, a column redundancy select signal is asserted when a set of redundant columns is selected. For a read operation, the column redundancy select signal propagates through redundant column logic select the appropriate data from a particular set of redundant columns. This redundant data that is selected is substituted for data stored in the memory array for the read operation.

Abstract: A memory device (50) contains a first array of memory (12) and a second array of memory (14). The arrays (12 and 14) are coupled to four segmented current data buses (iGDLs) (16, 18, 20, and 22). When in a x36 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate directly with output buffers (56-59) through several current-to-voltage converters (24-31). When in a x18 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate through the converts (24-31), through a voltage bus (52 and 54, see also FIG. 3), to the output buffers (56-59). The change in wiring for x36 word mode versus x18 word mode is done either by a top-level metal option in fabrication or by user software programming whereby the device (50) is easily wired into one of two configurations while maintaining an advantageous speed/power product.

Abstract: A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.