Abstract: A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

Abstract: A transistor has a JFET gate region of a first conductivity type formed at the face of a semiconductor layer to laterally and downwardly surround a drift region of a second conductivity type. A thick insulator region is formed on a portion of the drift region at the face. A IGFET body of the first conductivity type is formed at the face to be adjacent the JFET gate region. This body spaces a source region of the second conductivity type from the drift region. A drain region is formed at the face to be of the second conductivity type and to adjoin the drift region, and to be spaced from the IGFET body. A conductive gate extends over the face between the source region and the thick insulator region, with a thin gate insulator spacing the gate from the IGFET body.

Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12) . A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

Abstract: A transistor has a JFET gate region of a first conductivity type formed at the face of a semiconductor layer to laterally and downwardly surround a drift region of a second conductivity type. A thick insulator region is formed on a portion of the drift region at the face. A IGFET body of the first conductivity type is formed at the face to be adjacent the JFET gate region. This body spaces a source region of the second conductivity type from the drift region. A drain region is formed at the face to be of the second conductivity type and to adjoin the drift region, and to be spaced from the IGFET body. A conductive gate extends over the face between the source region and the thick insulator region, with a thin gate insulator spacing the gate from the IGFET body.