Patents by Inventor Wai Wong Chow
Wai Wong Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825757Abstract: Various example embodiments concern an integrated circuit (IC) package having a clip with a protruding tough-shaped finger portion. The clip can be used in various IC packages including, for example, soft-soldered compact power packages such as rectifiers with specified surge current capability. Such embodiments can be implemented to allow for a visual inspection capability of the soldering area for connecting a lead frame, via the clip, to a surface of the IC package die, while still providing sufficient thermal mass to limit the temperature increase during forward surge current loads. This results in a simple to manufacture design without compromising too much on performance.Type: GrantFiled: December 19, 2016Date of Patent: November 3, 2020Assignee: NEXPERIA B.V.Inventors: Haibo Fan, Pompeo v Umali, Tim Boettcher, Wai Wong Chow
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Patent number: 10658274Abstract: An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.Type: GrantFiled: December 17, 2018Date of Patent: May 19, 2020Assignee: Nexperia B.V.Inventors: Tim Boettcher, Haibo Fan, Wai Wong Chow, Pompeo V. Umali, Shun Tik Yeung, Chi Ho Leung
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Publication number: 20190189545Abstract: An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Tim BOETTCHER, Haibo FAN, Wai Wong CHOW, Pompeo V. UMALI, Shun Tik YEUNG, Chi Ho LEUNG
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Patent number: 10269751Abstract: A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.Type: GrantFiled: November 3, 2016Date of Patent: April 23, 2019Assignee: Nexperia B.V.Inventors: Wai Wong Chow, On Lok Chau
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Publication number: 20180174951Abstract: Various example embodiments concern an integrated circuit (IC) package having a clip with a protruding tough-shaped finger portion. The clip can be used in various IC packages including, for example, soft-soldered compact power packages such as rectifiers with specified surge current capability. Such embodiments can be implemented to allow for a visual inspection capability of the soldering area for connecting a lead frame, via the clip, to a surface of the IC package die, while still providing sufficient thermal mass to limit the temperature increase during forward surge current loads. This results in a simple to manufacture design without compromising too much on performance.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Inventors: Haibo Fan, Pompeo v. Umali, Tim Boettcher, Wai Wong Chow
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Publication number: 20180122763Abstract: A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.Type: ApplicationFiled: November 3, 2016Publication date: May 3, 2018Inventors: Wai Wong Chow, On Lok Chau
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Patent number: 7112871Abstract: A semiconductor device (10) includes a first leadframe (18) having a perimeter (20) that defines a cavity (22) and leads (14) extending inwardly from the perimeter, and a second leadframe (32) having top and bottom surfaces and a die paddle surrounding a die receiving area (36). An integrated circuit (12) is placed within the die receiving area of the second leadframe. The IC has bonding pads (44) located on a peripheral portion of its top surface. The second leadframe and the IC are in facing relation with the first leadframe such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads. A mold compound (50) is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC. At least the bottom surfaces of the leads are exposed.Type: GrantFiled: January 26, 2005Date of Patent: September 26, 2006Assignee: Freescale Semiconductor, INCInventors: Hei Ming Shiu, Wai Wong Chow, Qing-Chun He
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Patent number: 7056766Abstract: A method of packaging an integrated circuit die (12) includes the steps of forming an array of soft conductive balls (14) in a fixture (30) and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape (36). A first side of the IC die is attached to the balls with a die attach adhesive (16) and then wire bonding pads (20) on the die are electrically connected directly to respective balls with wires (22). An encapsulant (24) is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls.Type: GrantFiled: December 9, 2003Date of Patent: June 6, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Nan Xu
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Patent number: 7033866Abstract: A leadframe (20) for a semiconductor device includes a first leadframe portion (12) having a perimeter that defines a cavity (16) and a plurality of leads (14) extending inwardly from the perimeter and a first thickness. A second leadframe portion (18) is attached to the first leadframe portion (16). The second leadframe portion (18) has a die paddle (20) received within the cavity (16) of the first leadframe portion (12). The second leadframe portion (18) has a second thickness that is greater than a thickness of the first leadframe portion (12). Such a dual gauge leadframe is suitable especially for high power devices in which the die paddle acts as a heat sink.Type: GrantFiled: January 26, 2005Date of Patent: April 25, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Wai Wong Chow, Zhi-Gang Bai, Clem H. Brown
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Patent number: 6958261Abstract: An image sensor device includes a QFN type leadframe having a central die attach flag and an outer bonding pad area having a plurality of bonding pads. A sensor IC is attached to the flag. The IC has a first surface with an active area and a peripheral bonding pad area that includes bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the leadframe bonding pads, thereby electrically connecting the IC and the leadframe. Stud bumps are formed on the first surface of the IC and a transparent cover is disposed over the IC active area and resting on the stud bumps. The cover allows light to pass therethrough onto the IC active area. A mold compound is formed over the leadframe, wirebonds and a peripheral portion of the cover.Type: GrantFiled: October 14, 2003Date of Patent: October 25, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Wai Wong Chow, Man Hon Cheng, Wai Keung Ho
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Patent number: 6949816Abstract: A semiconductor component for electrical coupling to a substrate (230) includes: a semiconductor chip (110); a non-leaded leadframe (120) including a plurality of electrical contacts (130) located around a periphery (111) of the semiconductor chip; a first electrical conductor (140) electrically coupling together the semiconductor chip and the non-leaded leadframe; and a mold compound (210) disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts includes: a first surface (310) having a first surface area for electrically coupling to the semiconductor chip; and a second surface (320) opposite the first surface and having a second surface area for electrically coupling to the substrate, where the second surface area is larger than the first surface area.Type: GrantFiled: April 21, 2003Date of Patent: September 27, 2005Assignee: Motorola, Inc.Inventors: Clem H. Brown, Wai Wong Chow, Frank J. Mosna, Jr.
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Patent number: 6917097Abstract: A leadframe (20) for a semiconductor device includes a first leadframe portion (12) having a perimeter that defines a cavity (16) and a plurality of leads (14) extending inwardly from the perimeter and a first thickness. A second leadframe portion (18) is attached to the first leadframe portion (16). The second leadframe portion (18) has a die paddle (20) received within the cavity (16) of the first leadframe portion (12). The second leadframe portion (18) has a second thickness that is greater than a thickness of the first leadframe portion (12). Such a dual gauge leadframe is suitable especially for high power devices in which the die paddle acts as a heat sink.Type: GrantFiled: August 20, 2003Date of Patent: July 12, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Wai Wong Chow, Zhi-Gang Bai, Clem H. Brown
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Patent number: 6905910Abstract: An image sensor device includes a first, QFN type leadframe to which a sensor IC is electrically connected. A second leadframe is provided for holding a lens. A third leadframe is positioned between the first and second leadframes to appropriately space the IC from the lens. Multiple sensor devices are assembled at the same time by the use of leadframe panels.Type: GrantFiled: January 6, 2004Date of Patent: June 14, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Kam Fai Lee
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Patent number: 6875635Abstract: A semiconductor device 30 includes a base carrier 32, an adhesive material layer 36 and an integrated circuit die 34. The base carrier 32 has a top side and a bottom side, the top side having a central area for receiving the die 34 and a peripheral area surrounding the central area. The adhesive material layer 36 is disposed on the top side of the base carrier in an “X” shaped pattern. The “X” shaped pattern includes two bisecting lines. The two bisecting lines extend well beyond the central area and into the peripheral area of the base carrier top surface. The die 34 is attached to the base carrier 32 with the adhesive material layer 36 at the central area. Even after attachment of the die 34, the adhesive material 36 extends well beyond the die 34 and the central area into the peripheral area.Type: GrantFiled: March 29, 2004Date of Patent: April 5, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Man Hon Cheng, Wai Wong Chow, Wai Keung Ho
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Patent number: 6867072Abstract: A semiconductor device (10) includes a first leadframe (18) having a perimeter (20) that defines a cavity (22) and leads (14) extending inwardly from the perimeter, and a second leadframe (32) having top and bottom surfaces and a die paddle surrounding a die receiving area (36). An integrated circuit (12) is placed within the die receiving area of the second leadframe. The IC has bonding pads (44) located on a peripheral portion of its top surface. The second leadframe and the IC are in facing relation with the first leadframe such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads. A mold compound (50) is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC. At least the bottom surfaces of the leads are exposed.Type: GrantFiled: January 7, 2004Date of Patent: March 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Qing-Chun He
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Patent number: 6838751Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).Type: GrantFiled: March 6, 2002Date of Patent: January 4, 2005Assignee: Freescale Semiconductor Inc.Inventors: Man Hon Cheng, Wai Wong Chow, Fei Ying Wong
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Publication number: 20040207054Abstract: A semiconductor component for electrical coupling to a substrate (230) includes: a semiconductor chip (110); a non-leaded leadframe (120) including a plurality of electrical contacts (130) located around a periphery (111) of the semiconductor chip; a first electrical conductor (140) electrically coupling together the semiconductor chip and the non-leaded leadframe; and a mold compound (210) disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts includes: a first surface (310) having a first surface area for electrically coupling to the semiconductor chip; and a second surface (320) opposite the first surface and having a second surface area for electrically coupling to the substrate, where the second surface area is larger than the first surface area.Type: ApplicationFiled: April 21, 2003Publication date: October 21, 2004Applicant: Motorola, Inc.Inventors: Clem H. Brown, Wai Wong Chow, Frank J. Mosna
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Patent number: 6798074Abstract: A semiconductor device 30 includes a base carrier 32, an adhesive material layer 36 and an integrated circuit die 34. The base carrier 32 has a top side and a bottom side, the top side having a central area for receiving the die 34 and a peripheral area surrounding the central area. The adhesive material layer 36 is disposed on the top side of the base carrier in an “X” shaped pattern. The “X” shaped pattern includes two bisecting lines. The two bisecting lines extend well beyond the central area and into the peripheral area of the base carrier top surface. The die 34 is attached to the base carrier 32 with the adhesive material layer 36 at the central area. Even after attachment of the die 34, the adhesive material 36 extends well beyond the die 34 and the central area into the peripheral area.Type: GrantFiled: March 4, 2002Date of Patent: September 28, 2004Assignee: Motorola, Inc.Inventors: Man Hon Cheng, Wai Wong Chow, Wai Keung Ho
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Publication number: 20040178511Abstract: A semiconductor device 30 includes a base carrier 32, an adhesive material layer 36 and an integrated circuit die 34. The base carrier 32 has a top side and a bottom side, the top side having a central area for receiving the die 34 and a peripheral area surrounding the central area. The adhesive material layer 36 is disposed on the top side of the base carrier in an “X” shaped pattern. The “X” shaped pattern includes two bisecting lines. The two bisecting lines extend well beyond the central area and into the peripheral area of the base carrier top surface. The die 34 is attached to the base carrier 32 with the adhesive material layer 36 at the central area. Even after attachment of the die 34, the adhesive material 36 extends well beyond the die 34 and the central area into the peripheral area.Type: ApplicationFiled: March 29, 2004Publication date: September 16, 2004Inventors: Man Hon Cheng, Wai Wong Chow, Wai Keung Ho
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Publication number: 20040080029Abstract: An image sensor device includes a QFN type leadframe having a central die attach flag and an outer bonding pad area having a plurality of bonding pads. A sensor IC is attached to the flag. The IC has a first surface with an active area and a peripheral bonding pad area that includes bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the leadframe bonding pads, thereby electrically connecting the IC and the leadframe. Stud bumps are formed on the first surface of the IC and a transparent cover is disposed over the IC active area and resting on the stud bumps. The cover allows light to pass therethrough onto the IC active area. A mold compound is formed over the leadframe, wirebonds and a peripheral portion of the cover.Type: ApplicationFiled: October 14, 2003Publication date: April 29, 2004Inventors: Wai Wong Chow, Man Hon Cheng, Wai Keung Ho