Abstract: Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.