Patents by Inventor Waichirou Fujieda
Waichirou Fujieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6522182Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.Type: GrantFiled: August 27, 1999Date of Patent: February 18, 2003Assignee: Fujitsu LimitedInventors: Hiroyoshi Tomita, Naoharu Shinozaki, Nobutaka Taniguchi, Waichirou Fujieda, Yasuharu Sato, Kenichi Kawasaki, Masafumi Yamazaki, Kazuhiro Ninomiya
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Patent number: 6459641Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.Type: GrantFiled: April 16, 2001Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Waichirou Fujieda, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Takayuki Nagasawa
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Publication number: 20010043100Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.Type: ApplicationFiled: August 27, 1999Publication date: November 22, 2001Inventors: HIROYOSHI TOMITA, NAOHARU SHINOZAKI, NOBUTAKA TANIGUCHI, WAICHIROU FUJIEDA, YASUHARU SATO, KENICHI KAWASAKI, MASAFUMI YAMAZAKI, KAZUHIRO NINOMIYA
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Publication number: 20010021140Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.Type: ApplicationFiled: April 16, 2001Publication date: September 13, 2001Applicant: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Waichirou Fujieda, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Takayuki Nagasawa
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Patent number: 6246620Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.Type: GrantFiled: March 23, 2000Date of Patent: June 12, 2001Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Waichirou Fujieda, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Takayuki Nagasawa
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Patent number: 6191999Abstract: A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.Type: GrantFiled: December 18, 1997Date of Patent: February 20, 2001Assignee: Fujitsu LimitedInventors: Waichirou Fujieda, Shinya Fujioka, Tadao Aikawa
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Patent number: 6188640Abstract: A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the output timing of a data signal. An output buffer receives the output control signal and then outputs the data signal in accordance with an output internal clock signal. The phase of the output internal clock signal is advanced from that of the input internal clock signal. The output control circuit also includes a latency counter that generates the output control signal by counting the cycles of a second output internal clock signal, which is delayed from the first output internal clock signal.Type: GrantFiled: September 17, 1999Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Tadao Aikawa, Yasuharu Sato, Hiroyuki Kobayashi, Waichirou Fujieda
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Patent number: 6181174Abstract: A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.Type: GrantFiled: September 23, 1999Date of Patent: January 30, 2001Assignee: Fujitsu LimitedInventors: Waichirou Fujieda, Yasuharu Sato, Nobutaka Taniguchi, Hiroyoshi Tomita, Yasurou Matsuzaki
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Patent number: 6088291Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.Type: GrantFiled: January 29, 1999Date of Patent: July 11, 2000Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Waichirou Fujieda, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Takayuki Nagasawa