Abstract: A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.

Abstract: A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

Abstract: An architecture to perform a hash algorithm. Embodiments of the invention relate to the use of processor architecture logic to implement an addition operation of initial state information to intermediate state information as required by hash algorithms while reducing the contribution of the addition operation to the critical path of the algorithm's performance within the processor architecture.

Abstract: A network forwarding device includes at least one physical interface, a framer and a network processor having multiple processing engines arranged as: a preparation stage provided on a first microengine of a processor having plural microengines the preparation stage to prepare the packet for processing, a processing stage provided on a second microengine of the processor, the processing stage to perform at least one crypto operation on the packet and a final stage provided on a third microengine of the processor to perform validate the packet in accordance with security associations and a switch fabric.

Abstract: A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: A system for ciphering data for transmission by a communication device is provided. The system includes a memory device having a memory buffer a first access port connected to the memory buffer and a second access port connected to the memory buffer. The system also has a data processing processor connected to the first access port via a first bus and a ciphering processor connected to the second access port via a second bus. The first access port and the second access port each provide mutually independent access to the memory buffer. The second bus is not connected to the first bus. The data processing processor is adapted to receive the data and provide the data to the memory buffer over the first bus. The ciphering processor is adapted to retrieve the data from the memory buffer over the second bus, generate ciphered data from the data, generate integrity check information for the ciphered data using the data and provide the ciphered data to the memory buffer over the second bus.

Abstract: A high-performance, low-latency data retrieval system is disclosed using hash functions. Given a set of input data, the data retrieval system may generate one or more index values and a signature value according to a predetermined hash function. The index values may be applied to respective data arrays to access a data unit therein. The data unit may include signatures previously developed when populating the array. If a signature from the data unit matches the signature generated from the hash function, then the associated index may be applied to a second portion of the respective data array to retrieve requested data.

Abstract: A security policy database cache includes at least one primary table including signature values that indicate that a packet's security policy database information may be in the cache and at least one secondary table including cache entries having a selector, flags, security association information and an operation to perform on the corresponding packet for which a cache lookup was made.