Abstract: A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

Abstract: A jitter measurement technique utilizing a high-bandwidth undersampling voltage measurement instrument is presented. A trigger is derived from the a signal having a repetitive signal pattern. The signal is compared with a threshold at a plurality of times relative to the trigger during multiple repetitions of the signal pattern to produce measurement samples indicative of signal level relative to the threshold. The measurement samples are used to determine the probability of signal edge states as a function of time for the multiple repetitions. The probability of signal edge states are used to determine an edge probability density as a function of time. A histogram of signal state transition times can be prepared from the edge probability density. Mean deviation of edge transitions of the signal can be estimates, and standard deviation of edge transitions of the signal can be estimated to give the root-mean-square (rms) jitter of the signal.

Abstract: Tester edge placement accuracy (EPA) is important for testing of semiconductor component devices. The value of that accuracy is quantified to the device manufacturer in terms of yield loss and bad parts sold as good parts (escapes in DPM). A simulation is presented that models the tester accuracy, the device edge distribution and their interaction for a example device having an operating speed of 800 Mbps. The same model can be applied for microprocessors or other parts that operate near the limits of ATE performance. In an example given, the estimated losses due to lack of appropriate tester accuracy are considerable: with the estimated yields and selling prices for the example device, the model shows a value of over $1 M for every 1 ps of enhanced tester edge placement accuracy.