Patents by Inventor Wakako Takeuchi
Wakako Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8450787Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.Type: GrantFiled: October 20, 2011Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi
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Patent number: 8330206Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: GrantFiled: February 14, 2012Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
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Publication number: 20120139032Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: ApplicationFiled: February 14, 2012Publication date: June 7, 2012Inventors: Hiroshi AKAHORI, Wakako Takeuchi, Atsuhiro Sato
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Patent number: 8153487Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.Type: GrantFiled: March 10, 2010Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Wakako Takeuchi, Hiroshi Akahori, Murato Kawai
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Patent number: 8133782Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: GrantFiled: February 16, 2011Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
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Publication number: 20120032253Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.Type: ApplicationFiled: October 20, 2011Publication date: February 9, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi
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Patent number: 8071444Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.Type: GrantFiled: September 30, 2010Date of Patent: December 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi
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Publication number: 20110163368Abstract: A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Inventors: Wakako TAKEUCHI, Hiroshi Akahori, Atsuhiro Sato
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Publication number: 20110136330Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Inventors: Hiroshi AKAHORI, Wakako TAKEUCHI, Atsuhiro SATO
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Patent number: 7928496Abstract: A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.Type: GrantFiled: June 7, 2007Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Wakako Takeuchi, Hiroshi Akahori, Atsuhiro Sato
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Patent number: 7906804Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: GrantFiled: May 17, 2007Date of Patent: March 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
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Publication number: 20110020995Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.Type: ApplicationFiled: September 30, 2010Publication date: January 27, 2011Inventors: Hiroshi Akahori, Wakako Takeuchi
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Patent number: 7829950Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.Type: GrantFiled: February 26, 2008Date of Patent: November 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi
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Patent number: 7821056Abstract: A nonvolatile semiconductor memory device includes an array of nonvolatile memory cell transistors, each of which is configured such that a tunnel insulation film, a floating gate electrode, a floating gate insulation film and a control gate electrode are stacked on a surface of a semiconductor substrate. A mean roughness of an interface between a polysilicon, of which the floating gate electrode is formed, and the floating gate insulation film is 1.5 nm or less.Type: GrantFiled: September 20, 2007Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi
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Publication number: 20100184275Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.Type: ApplicationFiled: March 10, 2010Publication date: July 22, 2010Inventors: Wakako Takeuchi, Hiroshi Akahori, Murato Kawai
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Publication number: 20100102448Abstract: A semiconductor device according to one embodiment includes: a semiconductor element formed on a semiconductor substrate; a metal wiring formed above the semiconductor element; an amorphous silicon film formed above the semiconductor element, the amorphous silicon film being insulated from the metal wiring; and a metal diffusion blocking film formed above the amorphous silicon film, the metal diffusion blocking film having a property to suppress diffusion of metal atoms in the metal wiring.Type: ApplicationFiled: October 21, 2009Publication date: April 29, 2010Inventors: Hiroshi Akahori, Tooru Ichikawa, Wakako Takeuchi
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Patent number: 7651914Abstract: A manufacturing method of a nonvolatile semiconductor memory device including: providing a first insulating film and a silicon film on a semiconductor substrate; providing a fifth insulating film containing silicon and oxygen on the silicon film; providing a second insulating film containing silicon and nitrogen on the fifth insulating film; providing a third insulating film on the second insulating film, the third insulating film is composed of a single-layer insulating film containing oxygen or multiple-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, and relative dielectric constant of the single-layer insulating film and the stacked insulating film being larger than relative dielectric constant of a silicon oxide film; providing a fourth insulating film containing silicon and nitrogen on the third insulating film; and providing a control gate above the fourth insulating film.Type: GrantFiled: July 21, 2008Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Yoshio Ozawa
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Publication number: 20090218615Abstract: A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed on the charge storage layer, and a gate electrode formed on the second gate insulation film, the width between side surfaces of the second gate insulation film in the bit line direction being smaller than the width between side surfaces of the gate electrode in the bit line direction.Type: ApplicationFiled: March 3, 2009Publication date: September 3, 2009Inventors: Wakako TAKEUCHI, Hiroshi Akahori, Masaki Kondo
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Publication number: 20090194807Abstract: A semiconductor memory device includes: a semiconductor substrate; an element isolation trench formed on the semiconductor substrate so as to surround an element region in which a memory element is to be formed; a first gate insulating film formed on the element region of the semiconductor substrate; a charge storing layer formed on the first gate insulating film; a second gate insulating film formed on the charge storing layer; a control electrode formed on the second gate insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor substrate along a channel direction of the charge storing layer; a sidewall oxide film formed on a side surface of the element isolation trench; and an element isolation insulating film formed so as to fill the element isolation trench together with the element isolation insulation film; wherein the top surface of the sidewall oxide film is flush with or above the top surface of the first gate insulating film.Type: ApplicationFiled: October 11, 2007Publication date: August 6, 2009Inventors: Wakako Takeuchi, Hiroshi Akahori, Hiroki Yamashita
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Publication number: 20090011586Abstract: A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the second insulating film, and composed of a single-layer insulating film containing oxygen or a plural-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, relative dielectric constant thereof being larger than it of a silicon oxide film, a fourth insulating film provided on the third insulating film and contains silicon and nitrogen, a control gate provided above the fourth insulating film, and a fifth insulating film provided between the charge accumulation layer and the second insulating film or between the fourth insulating film and the control gate, and contains silicon and oxygen.Type: ApplicationFiled: July 21, 2008Publication date: January 8, 2009Inventors: Hiroshi Akahori, Wakako Takeuchi, Yoshio Ozawa