Abstract: A coupling circuit is disclosed having a series connection of a first transistor (2) and a controlled current source (3). A transmission line (17) is connected to the junction of the first transistor (2) and current source (3). A signal I/O terminal of a signal processing device (1), acting as both input and output, is connected via a first resistor (4) to the base of the first transistor (2). A control output S of the device (1), which presents a signal establishing the transmission direction, is connected via a second resistor (5) to the base of the first transistor (2). The transmission line (17) is connected via a third resistor (6) to the signal I/O terminal of the device (1). This coupling circuit can be used both for transmitting and for receiving signals, the impedance being low in the transmitting direction and high in the receiving direction.

Abstract: Amplitude-modulated carrier frequency oscillations are supplied to the demodulator of the present invention whose peak value is maintained constant on its receiving side by a controller. The carrier frequency oscillations are supplied via a capacitor to the two inputs of a NOR gate. Both inputs of the NOR gate are connected via a resistor with the output thereof. The output of the NOR gate is connected with an inverter, at whose output the evaluated carrier frequency oscillations in the form of data are collected. Because the different elements of C-MOS circuits inherently exhibit different threshold values, the comparator functions required for demodulation can be realized at little expense using the gates of a C-MOS circuit.

Abstract: A house system for the transmission of information messages which are encoded in the form of digital signals wherein a code is selected which facilitates the testing of each information bit, including a central station and a series of substations at which the information messages of the central station are selectively deliverable through the electrical power supply wiring as the transmission path which is utilized by further similar systems. Each substation, due to an erroneously recognized information bit, will terminate the further information evaluation, whereby each of the information messages evidences a selectable subsequence of digital signals which represents a house code which is specific with respect to the applicable house system, which preferably occurs near the beginning of the total sequence of digital signals representing the information message. The central station generates an operating signal when it is transmitting information messages which is received by a monitoring unit.

Abstract: A digital signal constituted by a stream of bits is so encoded that its running digital sum (RDS) is confined to a range defined by predetermined lower and upper permissible limits, i.e., absent transmission error. Instead of using a forwards-backwards digital counter to monitor the RDS, with its associated expense and relatively high power consumption when high transmission rates are involved, use is made of an analog integrator which integrates the digital signal to be monitored and generates an analog RDS signal. A digit-error signal is generated when the analog RDS signal attempts to exceed a predetermined analog value corresponding to the upper permissible limit of the RDS or to fall below a predetermined analog value corresponding to the lower permissible limit of the RDS.