Abstract: The invention relates to a method for determining a value of a current using a current transformer that operates in the core saturation region. A peak value detector determines a peak value of one half-cycle of the secondary current. The peak value is stored in a storage element for further processing. A comparator detects that the peak value has been reached. After this, the comparator supplies a switching signal to a signal processing unit, and this signal starts the signal processing unit. The signal processing unit receives the peak value that was stored in the storage element and provides this value for further processing. A RESET pulse is then transmitted to a switching apparatus to discharge the storage element and thus allow the detection of the next peak value.

Abstract: The invention relates to a method for determining a value of a current using a current transformer that operates in the core saturation region. A peak value detector determines a peak value of one half-cycle of the secondary current. The peak value is stored in a storage element for further processing. A comparator detects that the peak value has been reached. After this, the comparator supplies a switching signal to a signal processing unit, and this signal starts the signal processing unit. The signal processing unit receives the peak value that was stored in the storage element and provides this value for further processing. A RESET pulse is then transmitted to a switching apparatus to discharge the storage element and thus allow the detection of the next peak value.

Abstract: Switching device for the short-circuit and overload protection of a power switching circuit, including an input, an output, a first AND gate, a power amplifier, a current limiter circuit and a current sensor connected in series between the input and output, the first AND gate having an inverting input, a threshold value switch connected to the current sensor for producing a current sensor-shaped signal to be fed to the inverting input of the first AND gate, a digital switch-in retarder for delaying the arrival of the current sensor-shaped signal at the inverting input of the first AND gate by producing a given switch-in time lag for blocking the first AND gate until a given switch-off time lag has run out in case of short-circuits and overloads, the digital switch-in retarder including a second AND gate having a first input, a second input, a third inverting input and an output, and a first counter being after-connected to the second AND gate and having a pulse timing input, a resetting input and an output, t