Abstract: A method and apparatus for controlling the operating flow in a data processing installation having a memory control and a micro-program control, controlled by a central clock pulse generator, incorporates a monitoring and test device for monitoring events which interrupt the normal flow and for stopping the normal operation of said clock pulse generator and for instituting a special test cycle controlled by said clock pulse generator and for controlling the operating flow following said special test cycle in response to the results thereof.

Abstract: A control unit for a processor, which can be controlled by microprograms, in a data processing system utilizes a microprogram memory into which recordings can be made (writable control memory), which exibits an access time which is greater than the machine cycle. The apparatus has an address register which is connected to the selector inputs of the memory and a microcommand register which is connected to the information outputs of the microprogram memory. A decoder unit is connected to the register and serve to derive control signals for a processing unit of the processor from a microcommand in the microcommand register. A switching network is arranged between the microcommand register and the address register and serves to form the address of the following microcommand.