Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: A voltage controlled oscillator includes two gain stages to split the bias current and reduce phase noise.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interferer signal to reduce intermodulation distortion in the frequency band, wherein the attenuating occurs prior to anti-alias filtering of the baseband signal.

Abstract: A circuit in a wireless transmitter or other apparatus is automatically calibrated using a calibration circuit to accommodate provide a desired characteristic such as a filter response, where the component values of the filter circuit may vary such as in an integrated circuit. In one embodiment, the calibration circuit is coupled to one or more adjustable capacitors in the filter circuit to select a capacitor value so that the filter circuit exhibits the desired filter response. In one particular embodiment, the adjustable capacitor is charged in an RC circuit for each clock cycle at power up. The value of the adjustable capacitor is changed for each clock cycle until the capacitor charges to a level greater than or equal to predetermined reference voltage. When the capacitor is charged to a predetermined reference voltage, a desired capacitance value is indicated, and the adjustable capacitor is maintained at the desired capacitance value to provide the desired filter output.

Abstract: A system includes a transceiver having mixers, variable gain amplifiers, a modulator, a local oscillator and power amplifiers that may receive control signals generated by a Digital-to-Analog Converter (DAC). The DAC may include a multiplexer that receives digital values that are transferred to a DAC core, converted to analog values, and stored in sample-and-hold circuits. The one DAC may service multiple devices within the transceiver with control signals. A smart timer may generate select signals to the multiplexer and sample-and hold circuits to prioritize updating of the control signals.

Abstract: A system includes a transceiver having mixers, variable gain amplifiers, a modulator, a local oscillator and power amplifiers that may receive control signals generated by a Digital-to-Analog Converter (DAC). The DAC may include a multiplexer that receives digital values that are transferred to a DAC core, converted to analog values, and stored in sample-and-hold circuits. The one DAC may service multiple devices within the transceiver with control signals. A smart timer may generate select signals to the multiplexer and sample-and hold circuits to prioritize updating of the control signals.

Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.

Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.

Abstract: A current regenerative comparator. A pair of cross coupled inverters are coupled to an equalizing transistor, an input current mirror and a reference current mirror, such that current flowing in the input current mirror is compared to the current flowing in the reference current mirror.