Abstract: A system (10) is disclosed for testing a watchdog timer (22). The watchdog timer is associated with a system (14) which is controlled by a control program executed by a programmed processor (20) and which is monitored by a supervisory system (18) in which the watchdog timer generates an interruption signal (NMI) which interrupts the control program when the watchdog timer does not generate a reset signal within a time window measured from a last reset signal. The supervisory system contains a circuit coupled to the watchdog timer for initiating testing of the watchdog timer. The watchdog timer contains a circuit for disabling the generation of the interruption signal during testing of the watchdog timer. Furthermore, the watchdog timer contains a circuit for shutting down the system which is controlled by the control program when the control program does not resume normal operation in response to an interruption signal.