Abstract: A receiver circuit is disclosed. The receiver circuit includes a receiver antenna or a receiver antenna arrays oriented at a receiver orientation angle and configured to receive a plurality of RF signals transmitted from a transmitter circuit including a transmit antenna or a transmit antenna array oriented at a transmitter orientation angle. A controller A) calculates first and second AoAs based on a first signal at a first receiver antenna array, and calculates third and fourth AoAs based on a second signal at a second receiver antenna array, and/or B) calculates first and second AoDs based on a third signal from a first transmit antenna array, and calculates third and fourth AoDs based on a fourth signal from a second transmit antenna array. The controller also determines which of the first and second AoAs is correct, and/or determines which of the first and second AoDs is correct.

Abstract: A transceiver circuit is disclosed. The transceiver circuit includes an antenna, a receiver RF chain configured to receive a receiver RF signal from the antenna, a transmitter RF chain configured to transmit a transmitter RF signal to the antenna, and a controller configured to cause the receiver RF chain to receive a first distance estimate between the antenna and another transceiver circuit, to calculate a second distance estimate between the antenna and the other transceiver circuit, and to determine a range estimate between the antenna and the other transceiver circuit based on the first distance estimate and the second distance estimate.

Abstract: A transceiver circuit is disclosed. The transceiver circuit includes an antenna, a receiver RF chain configured to receive a receiver RF signal from the antenna, a transmitter RF chain configured to transmit a transmitter RF signal to the antenna, and a controller configured to cause the receiver RF chain to receive a first distance estimate between the antenna and another transceiver circuit, to calculate a second distance estimate between the antenna and the other transceiver circuit, and to determine a range estimate between the antenna and the other transceiver circuit based on the first distance estimate and the second distance estimate.

Abstract: A receiver circuit is disclosed. The receiver circuit includes one or more receiver antennas configured to receive a plurality of RF signals transmitted from a transmitter circuit including one or more transmit antennas, an RF chain configured to generate a plurality of digitized samples of the received RF signals, and a controller configured to receive the digitized samples, to calculate a plurality of additional samples, and to calculate a measured angle of arrival or angle of departure (AoA or AoD) of the RF signals based on the digitized samples and the calculated additional samples.

Abstract: A transceiver circuit is disclosed. The transceiver circuit includes an antenna, a receiver RF chain configured to receive a receiver RF signal from the antenna, a transmitter RF chain configured to transmit a transmitter RF signal to the antenna, and a controller configured to access a CFO (carrier frequency offset) estimate, and to, for each of one or more working frequencies: cause the receiver RF chain to receive a receiver RF signal from the antenna at each working frequency, generate I/Q measurement data based at least in part on the received receiver RF signal and the CFO estimate, store the I/Q measurement data, and cause the transmitter RF chain to transmit a transmitter RF signal to the antenna at each working frequency, where the controller is further configured to cause the transmitter RF chain to transmit the I/Q measurement data for each working frequency to the antenna.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Abstract: A transceiver circuit is disclosed. The transceiver circuit includes an antenna, a receiver RF chain configured to receive a receiver RF signal from the antenna, a transmitter RF chain configured to transmit a transmitter RF signal to the antenna, a frequency synthesizer configured to generate an oscillator signal, and a controller configured to cause the receiver RF chain to receive a first reflection signal from the antenna, down convert the first reflection signal to a non-zero intermediate frequency, and determine a range estimate to another transceiver circuit based on a phase of the first reflection signal.

Abstract: A transceiver is disclosed. The transceiver accesses a CFO (carrier frequency offset) estimate, and, for each of one or more working frequencies: transmits a transmitter RF signal at each working frequency, receives a receiver RF signal at each working frequency, and generates first I/Q measurement data based at least in part on the received receiver RF signal and the CFO estimate. In some embodiments, the transceiver receives I/Q measurement information for each working frequency. In some embodiments, the transceiver generates second I/Q measurement data based at least in part on the received I/Q measurement information. In some embodiments, the transceiver estimates a distance between the antenna and an antenna of another device based at least in part on the first and second I/Q measurement data.

Abstract: A receiver is disclosed. The receiver includes one or more antennas receiving signals from a transmitter including one or more antennas, and at least one RF chain generating digital samples based on the received signals. Either A) the signals are transmitted by a single antenna of the transmitter and are received by multiple antennas of the receiver, or B) the signals are transmitted by multiple antennas of the transmitter and are received by a single antenna of the receiver. The receiver also includes a controller determining a plurality of groups of digital samples to use for calculating estimates of an AoA or AoD of the received signals, calculate estimates of AoA or AoD based on the groups of digital samples, select a subset of the estimates, and calculate a measured AoA or AoD based on the selected subset of estimates.

Abstract: A receiver circuit is disclosed. The receiver circuit includes a receiver antenna or a receiver antenna arrays oriented at a receiver orientation angle and configured to receive a plurality of RF signals transmitted from a transmitter circuit including a transmit antenna or a transmit antenna array oriented at a transmitter orientation angle. A controller A) calculates first and second AoAs based on a first signal at a first receiver antenna array, and calculates third and fourth AoAs based on a second signal at a second receiver antenna array, and/or B) calculates first and second AoDs based on a third signal from a first transmit antenna array, and calculates third and fourth AoDs based on a fourth signal from a second transmit antenna array. The controller also determines which of the first and second AoAs is correct, and/or determines which of the first and second AoDs is correct.

Abstract: One inventive aspect is a receiver circuit. The receiver circuit includes a controller selecting a receiver antenna array and/or a transmit antenna array. The controller also calculates a first AoA and/or a first AoD based on signals from the selected receiver and/or transmit antenna array. The controller also, in response to the absolute value of the first AoA minus ?/2 not being less than or equal to the AoA threshold angle, selects a different receiver antenna array, and calculates a second AoA based on digitized samples of RF signals from the selected different receiver antenna array. The controller also, in response to the absolute value of the first AoD minus ?/2 not being less than or equal to the AoD threshold angle, selects a different transmit antenna array, and calculates a second AoD based on digitized samples of RF signals from the selected different transmit antenna array.

Abstract: A receiver circuit is disclosed. The receiver circuit includes one or more receiver antennas configured to receive a plurality of RF signals transmitted from a transmitter circuit including one or more transmit antennas, an RF chain configured to generate a plurality of digitized samples of the received RF signals, and a controller configured to receive the digitized samples, to calculate a plurality of additional samples, and to calculate a measured angle of arrival or angle of departure (AoA or AoD) of the RF signals based on the digitized samples and the calculated additional samples.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Abstract: A receiver is disclosed. The receiver includes one or more antennas receiving signals from a transmitter including one or more antennas, and at least one RF chain generating digital samples based on the received signals. Either A) the signals are transmitted by a single antenna of the transmitter and are received by multiple antennas of the receiver, or B) the signals are transmitted by multiple antennas of the transmitter and are received by a single antenna of the receiver. The receiver also includes a controller determining a plurality of groups of digital samples to use for calculating estimates of an AoA or AoD of the received signals, calculate estimates of AoA or AoD based on the groups of digital samples, select a subset of the estimates, and calculate a measured AoA or AoD based on the selected subset of estimates.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: Techniques are described for crest factor reduction in power amplifier circuits. For example, crest factor reduction can keep the peak signal level of a signal for transmission to below a peak threshold level associated with a power amplifier in the transmission path. The signal is received by the crest factor reduction system and clipped in accordance with the peak threshold level. Edge smoothing is then applied to the clipped signal to reduce out-of-band emissions. The edge smoothing is implemented by a moving average filter, such as a time-domain box filter. In some embodiments, a maximum operation or minimum operation is used to prevent signal peak regrowth after the filtering. Some embodiments also include various iteration loops to further improve crest factor reduction.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.