Abstract: A digital signal processing device includes at least one peripheral unit, a data bus and at least three data registers and a flag register exchanging binary-encoded data with the at least one peripheral unit through the data bus. Two shift registers are each loaded with contents of one of the data registers. Two modification units are each connected downstream stream of a respective one of the shift registers. An arithmetic and logic unit is connected to the modification units. A multiplication register is to be written by the arithmetic and logic unit and through the data bus by the at least one peripheral unit. A logic block controls shift operations of at least one of the two shift registers as a function of contents of the multiplication register. A programmable sequence control is connected to the data registers, the at least one peripheral unit, the arithmetic and logic unit, the flag register, the shift registers, and the modification units.