Abstract: A data processing system includes an embedded controller (100) having a core (102), a system bus, nonvolatile memory (104), and random access memory (RAM) (106). The RAM (104) has a non-overlay region (108) and an overlay region (110). The overlay region (110) may be divided into a plurality of partitions. Partitions of the overlay region (110) may be used as general purpose memory when they are not being used as overlay regions.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: A data processing system (20) has a central processing unit (CPU) (22) and a memory (30) for storing an exception table. The exception table is mapped in the memory (30) in consecutive segments, with each segment for storing a predetermined number of instructions for executing the exception. By asserting a control bit, the exception table can be relocated, or remapped, and compressed into a jump table. The jump table stores only jump instruction for branching to the exception routines, which are relocated to other memory locations. The jump table is generated from the starting addresses of the exception routines. Relocating the exception routines allows for more efficient use of internal memory space of the data processing system (20).

Abstract: A method and apparatus for providing an external indication of internal cycles in a data processing system (10) in order to more easily debug software being executed by data processing system (10). In one embodiment, data processing system (10) provides cycle type signals (14) external to data processing system (10). The cycle type signals (14) can be used to determine a variety of information about the activity and bus cycles being performed within data processing system (10), activity which is not readily discernible except by way of the cycle type signals (14). In some cases the information provided by the cycle type signals (14) is sufficient for debug purposes; in other cases, information from additional signals, e.g. the address type signals (15) and the read/write signal (19) may also be required.

Abstract: A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.

Abstract: A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.

Abstract: The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.

Abstract: When a data processing system (10) is reset, a configuration value is determined by either an external configuration value provided to a plurality of external integrated circuit pins or an internal value stored in an internal memory of the system (30, 60). If an external configuration value is not provided and if an internal value is not stored in the internal memory, the data processing system provides a default configuration value. The default configuration value is stored in a memory in a system integration unit (20). Configuration data may also be retrieved from the external integrated circuit pins in octal packets. A last bit of each octal packet determines whether a next eight bits of the configuration data is to be retrieved via the plurality of integrated circuit pins or to be retrieved from the default configuration value stored in the system integration unit of the data processing system.

Abstract: A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).

Abstract: An integrated circuit data processor (30) includes a central processing; unit (31) with separate internal instruction (32) and load/store (33) buses. The data processor (30) includes a nonvolatile memory (34) connected to the instruction bus (32). In a first mode of operation, a system integration unit (36) allows cross-bus accesses from the load/store bus (33) to the nonvolatile memory (34) on the instruction bus (32). These cross-bus accesses allow the central processing unit (31) to access system parameters from the same nonvolatile memory (34) which stores the program. In a second mode of operation, a control bit in the system integration unit (36) routes accesses from the load/store bus (33) to the nonvolatile memory (34) off-chip. The central processing unit (31) continues to access instructions from the nonvolatile memory (34) in the second mode. In this way, system parameters normally stored in the nonvolatile memory (34) may be accurately calibrated.

Abstract: A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.

Abstract: A data processor has a test mode which may be selectively accessed for either production testing of the processor or user testing from an external control signal. To enter the test mode, both an external signal applied to an integrated circuit package pin of the data processor and a register bit must be asserted. If only the register bit is asserted, the special mode cannot be entered until the data processor has been reset again.