Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Abstract: Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Abstract: The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit.The input and output sections each contain (almost) twice the number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site.

Abstract: The invention comprises circuitry for detecting relatively small amounts of charge emitted from a CCD register. The circuit acts as a differential amplifier, differentiating between charge levels corresponding to logical zeros and logical ones and generates corresponding system level logic signals. A reference charge is developed by a self-tracking reference charge injector. Both the reference charge and the charge packet to be sensed are coupled to the differential amplifier via buffering diode-coupled transistors. The circuit provides for a REFRESH mode of operation, but may be modified to also allow for READ, WRITE or PARTIAL-WRITE modes of operation.

Abstract: The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two-phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain the same number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site.

Abstract: Interface circuitry for a charged coupled device (CCD) register system. The circuitry enables a PARTIAL-WRITE mode of operation on a CCD storage register. A data bus, which may be bi-directional, is coupled to the sense amplifier of the CCD storage register. The coupling is via interface circuitry responsive to control signals for enabling the register and also enabling a WRITE operation. Discontinuation of the WRITE signals frees the data bus for other uses, thereby allowing for a PARTIAL-WRITE mode of operation. The interface circuitry is simplified so as to require a minimum of space, thereby enhancing the density characteristics of the CCD storage system.

Abstract: The invention comprises a CCD memory chip. A CCD chip is comprised of a plurality of arrays, each of which is in turn comprised of a plurality of CCD registers. A serial addressing system may be used to determine which of the arrays is accessed. Fault-tolerance with respect to defective arrays is achieved by the combination of having only the address circuits for properly functioning arrays form the bits of an N-bit addressing shift register, (whereas the address circuits for improperly functioning arrays are shorted such that they do not form a bit of the N-bit address shift register,) and disabling the voltage delivered to a faulty array. The control circuitry includes the address circuitry and further includes means for controllably providing power to the array components. A plurality of arrays comprises a chip having pads for connecting the chip to the rest of the system.

Abstract: A device for injecting precisely controlled amounts of charge corresponding to data bits, into charge-coupled device registers. The device converts input signals in the form of logic level voltages into relatively small packets of charge. The device allows for relatively large variations at its input terminal, yet still produces highly controlled levels of charge at its output terminal. The output level of charge is also highly controlled despite variations in process parameters for a semiconductor wafer.