Patents by Inventor Wallace Edwards
Wallace Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933859Abstract: In some examples, apparatus comprises a multiplexer (MUX) adapted to be coupled to a set of battery cells and configured to provide a voltage of a different battery cell in the set of battery cells based on a MUX control signal. Apparatus comprises a comparator coupled to the MUX and configured to compare a MUX output signal to a threshold voltage to provide a comparator output signal. Apparatus comprises a digital control circuit configured to provide the MUX control signal to the MUX, to store the comparator output signal, and to use a logic AND gate to provide an AND gate output signal based on the stored comparator output signal.Type: GrantFiled: June 30, 2021Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradford Lawrence Hunter, Eric Frank Estes, Wallace Edward Matthews
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Publication number: 20230003810Abstract: In some examples, apparatus comprises a multiplexer (MUX) adapted to be coupled to a set of battery cells and configured to provide a voltage of a different battery cell in the set of battery cells based on a MUX control signal. Apparatus comprises a comparator coupled to the MUX and configured to compare a MUX output signal to a threshold voltage to provide a comparator output signal. Apparatus comprises a digital control circuit configured to provide the MUX control signal to the MUX, to store the comparator output signal, and to use a logic AND gate to provide an AND gate output signal based on the stored comparator output signal.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Bradford Lawrence HUNTER, Eric Frank ESTES, Wallace Edward MATTHEWS
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Patent number: 10939670Abstract: A beehive including a plurality of hive bodies including a base hive body and at least one upper hive body. There are a plurality of frames positioned in each hive body with a pinning device coupled to a hive body. The hive body has a plurality of holes spaced along a side of the hive body. The pinning device is inserted through at least one of the holes to contact a frame inside the hive body to thereby inhibit shifting of the frame relative to the hive body.Type: GrantFiled: January 29, 2019Date of Patent: March 9, 2021Assignee: Key Partners Group, Inc.Inventor: Wallace Edward Gibson
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Publication number: 20200236910Abstract: A beehive including a plurality of hive bodies including a base hive body and at least one upper hive body. There are a plurality of frames positioned in each hive body with a pinning device coupled to a hive body. The hive body has a plurality of holes spaced along a side of the hive body. The pinning device is inserted through at least one of the holes to contact a frame inside the hive body to thereby inhibit shifting of the frame relative to the hive body.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Applicant: Key Partners Group Inc.Inventor: Wallace Edward Gibson
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Patent number: 9407250Abstract: The disclosure presented herein provides example embodiments of systems for accurate multiplexing. The systems and methods presented may be suitable for non-limiting examples of analog to digital conversion with a switched input voltage (for a switched capacitor application) or any circuit with high voltage/high accuracy voltage multiplexing. In an example embodiment, pulsed current sources may be implemented to rapidly turn on and turn off the selected and unselected multiplexer ports while maintaining relatively low power consumption. A Kelvin input port may allow a high voltage input to be accurately sensed by avoiding a voltage drop associated with a selected pass gate p-channel FET channel resistance and parasitic wire resistance. The Kelvin input port biases the gate of a pass FET structure whose body terminals are allowed to remain floating.Type: GrantFiled: February 5, 2010Date of Patent: August 2, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradford Lawrence Hunter, Richard David Nicholson, Wallace Edward Matthews
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Publication number: 20120070898Abstract: The iCell is a newly-created cell that is incubated and harvested using sprouted barley grain (or other gluten grains) along with clover seeds, pepper seeds, alfalfa water, and a live yeast sponge. An electrical current is used to stimulate the curing process to solidify the iCell in a contained field. The iCell is a consistently-propagated cell that allows nutrition to be more completely utilized in the human body. This nutrition represented by Cellionose and enhanced amino acids allows for the creation of healthy cells throughout the body. The iCell is identified as a new cellular organism whose properties have been encountered randomly throughout humanity's history. This patent outlines the production of consistently-propagated cells. At a cellular level the iCell has far-reaching applications including water reclamation, water desalination, human hydration, and unique polypeptide bonding creating new amino acids. ICells have a direct correlation with the measurable potential for hydrogen.Type: ApplicationFiled: August 5, 2011Publication date: March 22, 2012Inventors: Carolyn Flora Anne Dean, Jeffrey Wallace Edwards
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Publication number: 20120064178Abstract: Cell-8 Solution is an intravenous solution introduced into the veins of the patient. Cell-8 Solution provides the cells of the body with highly absorbed minerals as well as new RNA information which changes the relationship of the body to the cancer in question. Treatment with Cell-8 Solution will prevent the body from accepting the existence of cancer cells so that cancer cell replication will no longer occur. Although intravenous Cell-8 Solution is superior, other applications include nebulized, transdermal and oral.Type: ApplicationFiled: June 21, 2011Publication date: March 15, 2012Inventors: Carolyn Flora Anne Dean, Jeffrey Wallace Edwards
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Patent number: 8134401Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.Type: GrantFiled: March 22, 2010Date of Patent: March 13, 2012Assignee: Texas Instruments IncorportedInventors: Bradford Lawrence Hunter, Wallace Edward Matthews
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Patent number: 7999710Abstract: A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.Type: GrantFiled: September 15, 2009Date of Patent: August 16, 2011Assignee: Texas Instruments IncorporatedInventors: Wallace Edward Matthews, Bertan Bakkaloglu, Brian Phillip Lum-Shue-Chan
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Publication number: 20110089977Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.Type: ApplicationFiled: March 22, 2010Publication date: April 21, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradford Lawrence Hunter, Wallace Edward Matthews
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Publication number: 20110089992Abstract: The disclosure presented herein provides example embodiments of systems for accurate multiplexing. The systems and methods presented may be suitable for non-limiting examples of analog to digital conversion with a switched input voltage (for a switched capacitor application) or any circuit with high voltage/high accuracy voltage multiplexing. In an example embodiment, pulsed current sources may be implemented to rapidly turn on and turn off the selected and unselected multiplexer ports while maintaining relatively low power consumption. A Kelvin input port may allow a high voltage input to be accurately sensed by avoiding a voltage drop associated with a selected pass gate p-channel FET channel resistance and parasitic wire resistance. The Kelvin input port biases the gate of a pass FET structure whose body terminals are allowed to remain floating.Type: ApplicationFiled: February 5, 2010Publication date: April 21, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradford Lawrence Hunter, Richard David Nicholson, Wallace Edward Matthews
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Publication number: 20110063146Abstract: A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Wallace Edward Matthews, Bertan Bakkaloglu, Brian Phillip Lum-Shue-Chan
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Patent number: 6577135Abstract: A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104).Type: GrantFiled: April 9, 2002Date of Patent: June 10, 2003Assignee: Texas Instruments IncorporatedInventors: Wallace Edward Matthews, David Louis Freeman, John Edward Landau
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Patent number: 6369576Abstract: A battery charging system is provided which is comprised of a battery pack (30) and a charging system (20). The battery pack (30) includes a battery (10) and a battery capacity detect circuit (32). The battery capacity detect circuit (32) having a memory is interfaced with the charging system (20) through a communication link to output a CHG-Bar signal. The battery capacity detect circuit (32) is operable to perform numerous monitoring operations on the battery by detecting the charge input to the battery and detecting charge taken away from the battery in a discharge operation. This operation is performed independent of the charging operation by the charging system (20). However, the charging operation of the charger (22) can be affected with the CHG-Bar signal.Type: GrantFiled: February 3, 1997Date of Patent: April 9, 2002Assignee: Texas Instruments IncorporatedInventors: Wallace Edward Matthews, David Louis Freeman, John Edward Landau
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Patent number: 6107802Abstract: A battery charging system is provided which is comprised of a battery pack (30) and a charging system (20). The battery pack (30) includes a battery (10) and a battery capacity detect circuit (32). The battery capacity detect circuit (32) is interfaced with the charging system (20) through a single line to output a CHG-Bar signal. The battery capacity detect circuit (32) is operable to perform numerous monitoring operations on the battery by detecting the charge input to the battery and detecting charge taken away from the battery in a discharge operation. This operation is performed independent of the charging operation by the charging system (20). However, the charging operation of the charger (22) can be affected with the CHG-Bar signal.Type: GrantFiled: October 19, 1998Date of Patent: August 22, 2000Inventors: Wallace Edward Matthews, David Louis Freeman, John Edward Landau
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Patent number: 5965997Abstract: A battery charge/discharge monitor circuit (10) is operable to be disposed in a battery pack (12) which can be connected to a battery (13). The monitor circuit (10) is operable to be connected to an external CPU (24) or similar system through a single wire communication port (22) for transferring information back and forth. There is also provided an external signal on a line (30) for indicating charge or discharge activity in the monitor circuit (10). The monitor circuit (10) is operable to collect information regarding the amount of charge input to the battery and the length of time that the charge is input to the battery and also the amount of charge that is removed from the battery and the length of time that the charge is removed. This information is stored in a memory block (62) for later access by the external CPU (24). This system also provides offset information to provide some type of compensation for non-linearities of the part.Type: GrantFiled: August 20, 1997Date of Patent: October 12, 1999Assignee: Benchmarq MicroelectronicsInventors: Milad Alwardi, Wallace Edward Matthews, Dave Heacock, David Louis Freeman
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Patent number: 5859560Abstract: A temperature compensated current source for driving a multi-vibrator (19) includes a voltage generator (10) that outputs a voltage that is proportional to absolute temperature (PTAT) and a resistor (12) for setting the current output by the voltage generator (10). The temperature coefficient of the resistor (12) is chosen such that any variations in the current supplied by the voltage generator (10) are compensated for to result in a current that has substantially no temperature variation. This current is mirrored to a current source (18) for driving the multi-vibrator (19). The voltage across the resistor (12) is a function of temperature, with the current being a function of the value of the resistor (12). The temperature coefficient of the resistor (12) is substantially equal to the temperature coefficient of the voltage generator (10) to yield a temperature coefficient of substantially 0 ppm/.degree. C. for the current.Type: GrantFiled: February 18, 1997Date of Patent: January 12, 1999Assignee: Benchmarq Microelectroanics, Inc.Inventor: Wallace Edward Matthews
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Patent number: 5205211Abstract: A method of printing with at least two printing plates, or their equivalent, characterized in that associated halftone dots belonging to two distinct pluralities, each of which is printed with one of said two printing plates, and each of which are interleaved with the other and printed in a color different from the other, are separated by a gap when printed in perfect register.Type: GrantFiled: December 23, 1991Date of Patent: April 27, 1993Inventor: Wallace Edwards
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Patent number: 5074206Abstract: A method of printing with at least two printing plates, or their equivalent, characterized in that associated halftone dots belonging to two distinct pluralities, each of which is printed with one of said two printing plates, and each of which are interleaved with the other and printed in a color different from the other, are separated by a gap when printed in perfect register.Type: GrantFiled: March 11, 1991Date of Patent: December 24, 1991Inventor: Wallace Edwards
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Patent number: 4998962Abstract: A method of printing with at least two printing plates, or their equivalent, characterized in that associated halftone dots belonging to two distinct pluralities, each of which is printed with one of said two printing plates, and each of which are interleaved with the other and printed in a color different from the other, are separated by a gap when printed in perfect register.Type: GrantFiled: January 25, 1989Date of Patent: March 12, 1991Inventor: Wallace Edwards