Abstract: An image frame transmission method for use in a network transmission system is provided. The network transmission system includes an image sensor and an image processor. Firstly, a first image data segment of an image frame captured by the image sensor is outputted to the image processor in response to a first state of a control signal after an initial signal has been asserted by the image processor. Then, the output of a second image data segment of the image frame following the first image data segment to the image processor is delayed in response to the transition of the control signal from the first state to a second state. Afterward, the second image data segment is outputted to the image processor in response to the transition of the control signal from the second state to the first second state.

Abstract: In a method for sampling image data from an image frame with component video, the image frame includes a first component frame, a second component frame and a third component frame. The method comprises steps of selecting a first component portion, a second component portion and a third component portion from the first component frame, the second component frame and the third component frame, respectively; and operating the first component portion, the second component portion and the third component portion to obtain a sampled unit arranged as a block array. The sampled unit includes at least a first component blocks derived from the first component portion, a second component block derived from the second component portion and a third component block derived from the third component portion.

Abstract: In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.

Abstract: A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A×B pixels, each of the image blocks having N×M pixels, wherein N is less than A and M is less than B. Next, a selected image block is outputted by selecting one of the image blocks as the selected image block. After that, a compressed image block is produced by storing the selected image block and compressing the selected image block. The step of outputting the selected image block and the step of producing the compressed image block are repeated until the image blocks are compressed into a plurality of compressed image blocks. Finally, a compressed image file is produced according to the compressed image blocks.

Abstract: An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.

Abstract: A circuit module of a memory card is selectively used with card readers/writers compliant with different access protocols. The circuit module includes a shared non-volatile memory; a first transmission control unit communicable with a first card reader/writer for controlling data transmission from/to the first card reader/writer; a second transmission control unit communicable with a second card reader/writer for controlling data transmission from/to the second card reader/writer; and a data buffer and memory access controller coupled to the non-volatile memory and the first and second transmission control units for conducting a data transmission path between a designated transmission control unit and the non-volatile memory, thereby allowing data transmission between the designated card reader/writer and the non-volatile memory. The circuit module can be grouped with different carrier housings to produce a memory card kit.

Abstract: An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.

Abstract: In a method for sampling image data from an image frame with component video, the image frame includes a first component frame, a second component frame and a third component frame. The method comprises steps of selecting a first component portion, a second component portion and a third component portion from the first component frame, the second component frame and the third component frame, respectively; and operating the first component portion, the second component portion and the third component portion to obtain a sampled unit arranged as a block array. The sampled unit includes at least a first component blocks derived from the first component portion, a second component block derived from the second component portion and a third component block derived from the third component portion.

Abstract: A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A×B pixels, each of the image blocks having N×M pixels, wherein N is less than A and M is less than B. Next, a selected image block is outputted by selecting one of the image blocks as the selected image block. After that, a compressed image block is produced by storing the selected image block and compressing the selected image block. The step of outputting the selected image block and the step of producing the compressed image block are repeated until the image blocks are compressed into a plurality of compressed image blocks. Finally, a compressed image file is produced according to the compressed image blocks.

Abstract: In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.

Abstract: An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.

Abstract: A circuit module of a memory card is selectively used with card readers/writers compliant with different access protocols. The circuit module includes a shared non-volatile memory; a first transmission control unit communicable with a first card reader/writer for controlling data transmission from/to the first card reader/writer; a second transmission control unit communicable with a second card reader/writer for controlling data transmission from/to the second card reader/writer; and a data buffer and memory access controller coupled to the non-volatile memory and the first and second transmission control units for conducting a data transmission path between a designated transmission control unit and the non-volatile memory, thereby allowing data transmission between the designated card reader/writer and the non-volatile memory. The circuit module can be grouped with different carrier housings to produce a memory card kit.

Abstract: An image frame transmission method for use in a network transmission system is provided. The network transmission system includes an image sensor and an image processor. Firstly, a first image data segment of an image frame captured by the image sensor is outputted to the image processor in response to a first state of a control signal after an initial signal has been asserted by the image processor. Then, the output of a second image data segment of the image frame following the first image data segment to the image processor is delayed in response to the transition of the control signal from the first state to a second state. Afterward, the second image data segment is outputted to the image processor in response to the transition of the control signal from the second state to the first second state.

Abstract: There is provided a method and device of minimizing the number of LDRQ signal pin of a LPC host. At least one of LPC devices requiring to perform DMA transmission or bus master request includes a LDRQ controller serving as a LDRQ control device. The LDRQ control device is connected with a plurality of LPC devices, wherein the LDRQ controller includes a decoding circuit for decoding LDRQ signals into DRQ signals, the DRQ signals are arbitrated by a DRQ control circuit to resolve their priorities, and the DRQ signal having the highest priority is transferred to an encoding circuit to be translated into a LDRQ signal. This LDRQ signal is transferred to either the LDRQ control device of next stage or LDRQ pin of LPC host so that only a single LPC pin is required by LPC host, and thereby the number of LDRQ signal pin of LPC host can be minimized and its manufacturing cost can be lowered.

Abstract: An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.