Abstract: A method of performing instruction marking in a computer processor architecture includes fetching instructions from a memory unit by a fetching unit in the computer processor architecture. Instruction groups for marking are determined. Fetched instructions are matched to instruction groups for marking. The fetched instructions are marked. Some of the marked instructions are selectively unmarked. The marked and unmarked instructions are forwarded to a queue of instructions for processing in the computer processor architecture.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.