Abstract: A computer-implemented method capable of evaluating a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed is provided. The method may include receiving parameters relating to the transistor, receiving parameters relating to an interconnection, receiving parameters relating to the plasma-based process, assigning first potentials to terminals of the transistor, calculating second potentials at the terminals of the transistor, and determining a degradation state of the transistor according to the second potentials at the terminals of the transistor.

Abstract: A method for preparing a non-reference transistor test structure having multiple terminals is disclosed. The method may include when an intended application of the non-reference transistor test structure is not for monitoring a plasma-involved charging, employing a protection mechanism by placing the MOSFET-based gated diode at a first metal layer, wherein the first metal layer is a lowermost metal layer, and when the intended application of the non-reference transistor test structure is for monitoring a plasma-involved charging, placing a charging monitoring antenna at a second metal layer; and employing the protection mechanism by placing a MOSFET-based gated diode at one metal layer above the second metal layer.

Abstract: A computer-implemented method capable of preparing a design rule indicative of a terminal metal area size of a transistor, minimizing a plasma-induced charging effect to the transistor in a plasma-based process for a dielectric layer performed on a metal layer above the transistor, is provided. The method includes a non-transitory computer readable medium, a design rule generator engine possessing a capability of accurately and swiftly simulating, evaluating and delivering design solutions for interconnect metals and dielectrics while largely saving test chip layout space, and performing the design-for-manufacturing process based on minimized plasma-induced charging effect to the transistor of the integrated circuit design. The disclosed method is applicable to all metal layers in the plasma-based process.

Abstract: An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.

Abstract: A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.

Abstract: A method for preparing a non-reference transistor test structure having multiple terminals is disclosed. The method may include when an intended application of the non-reference transistor test structure is not for monitoring a plasma-involved charging, employing a protection mechanism by placing the MOSFET-based protection device at a first metal layer, wherein the first metal layer is a lowermost metal layer, and when the intended application of the non-reference transistor test structure is for monitoring a plasma-involved charging, placing a charging monitoring antenna at a second metal layer; and employing the protection mechanism by placing a MOSFET-based protection device at one metal layer above the second metal layer.

Abstract: A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.

Abstract: A computer-implemented method capable of minimizing a plasma-induced charging effect to a transistor in a plasma-based process is provided. The plasma-based process is for a dielectric layer on the transistor and a metal layer is formed above the dielectric layer. The method may include calculating difference in potential between a gate terminal and a remaining terminal of the transistor, and determining whether an absolute value of the potential at the gate terminal is larger than an absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds a degradation threshold.

Abstract: A computer-implemented method capable of preparing a design rule indicative of a terminal metal area size of a transistor in a plasma-based process is provided. The method include calculating potentials of terminals at a first side and a second side of the transistor using a plasma-charging-effect function associated with the terminal at the first side, and plasma-charging-effect functions associated with the terminals at the second side. The method may further determine difference in potential between the terminal at the first side and the terminals at the second side to further determine whether such difference exceeds a degradation threshold, before determining a metal area size for the terminal. The disclosed method is applicable to all metal layers in the plasma-based process.

Abstract: A computer-implemented method capable of evaluating a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed is provided. The method may include receiving parameters relating to the transistor, receiving parameters relating to an interconnection, receiving parameters relating to the plasma-based process, assigning first potentials to terminals of the transistor, calculating second potentials at the terminals of the transistor, and determining a degradation state of the transistor according to the second potentials at the terminals of the transistor.

Abstract: A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.

Abstract: A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided.

Abstract: A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided.

Abstract: A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.

Abstract: The present invention provides a novel solution for simultaneously extracting the properties of the interconnect wires and the inter-wire dielectrics exposed to the IC planarization process.

Abstract: A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

Abstract: A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).