Abstract: A method for measuring a metal surface treatment of a metal component includes creating a solid model of the metal component, identifying surface locations on the metal component at which a set of structural properties is specified by design, and identifying a simulated location on the solid model corresponding to the identified surface location on the metal component. The method includes preparing a simulation fixture plan for fabricating a simulation fixture having an element for supporting a test strip holder thereon at the identified simulated location, and then fabricating the simulation fixture. A test strip holder is positioned at the identified simulated location on the simulation fixture, and a test strip is positioned in the test strip holder. The simulation fixture is subjected to the metal surface treatment wherein the simulation fixture has the test strip holder positioned thereon and the test strip holder has the test strip positioned thereon.

Abstract: A protected test strip holder according to the present invention includes a test strip holder onto which a test strip, such as for example an Almen strip, may be mounted using fasteners provided on the test strip holder. A protective covering is form-fitted to the test strip holder and, optionally, to the test strip holder having a test strip mounted thereon. The present invention also comprises a method for protecting and storing a test strip holder that includes providing a test strip holder, forming or molding a protective covering form-fitting to the test strip holder, and placing the protective covering over the test strip holder. The test strip holder may have a test strip mounted thereon prior to molding the form-fitting protective covering.

Abstract: Fluorescence immunoassays methods are provided which use fluorescent dyes which are free of aggregation and serum binding. Such immunoassay methods are thus, particularly useful for the assay of biological fluids, such as serum, plasma, whole blood and urine.

Abstract: Fluorescent dyes which are free of aggregation and serum binding are provided. These dyes are suitable for applications such as fluorescence immunoassays, in vivo imaging and in vivo tumor therapy.

Abstract: Light, pulsed or continuous at a wavelength (e.g. 780 nm), fluoresceces a specimen. The specimens may be combinations of a dye (preferably labelled), an antigen (e.g. rubella) and an antibody reactive with the antigen, with properties of polarizing the light when fluoresced. The light polarized in a first direction (e.g. z-axis) parallel to the incident light and in a second direction (e.g. x-axis) perpendicular to the incident light are measured. A second specimen is then provided with the antigen and the antibody but without the dye. The same light as discussed above fluoresces the second specimen and polarizes the light when fluoresced. The light polarized in the first (z-axis) and second (x-axis) directions in the second specimen is measured. These measurements are processed in a microprocessor with the measurements in the z and x directions in the first specimen to identify the antigen or, when the antigen is known, to identify the concentration of the antigen in the first specimen.

Abstract: A master-slave processor interface protocol transfers a plurality of instructions from a master processor to a slave processor. Each instruction has an opcode and a set of operands. The interface includes a micro-engine which sends the opcode for each of the instructions to be executed to the slave processor and stores the opcode in a first buffer in the slave processor. A second micro-engine operates the master processor to fetch and process the set of operands for each of the instructions to be executed by the slave processor in the order of the opcode delivery to the first buffer. A third micro-engine delivers a signal to the slave processor when the master processor is ready to deliver the operands for an instruction. The opcode associated with the operands ready to be delivered is then moved from the first buffer to a second buffer upon receiving the signal from the master processor. The processed set of operands are then sent to the second buffer and the instruction is executed.

Abstract: During the operation of a computer system whose processor is supported by virtual cache memory, the cache must be cleared and refilled to allow the replacement of old data with more current data. The cache is filled with either P or N (N>P) blocks of data. Numerous methods for dynamically selecting N or P blocks of data are possible. For instance, immediately after the cache has been flushed, the miss is refilled with N blocks, moving data to the cache at high speed. Once the cache is mostly full, the miss tends to be refilled with P blocks. This maintains the currency of the data in the cache, while simultaneously avoiding writing-over of data already in the cache. The invention is useful in a multi-user/multi-tasking system where the program being run changes frequently, necessitating flushing and clearing the cache frequently.

Abstract: A method and arrangement for siloing information in a computer system uses a smaller number of large-size latches by providing a timing silo having a set of n timing state devices sequentially connected for receiving and siloing at least one bit. The arrangement has an information silo having a set of p information state devices which are sequentially connected for receiving and siloing information. These information state devices have device enables coupled to separate locations in the timing silo so that a bit at a particular location in the timing silo enables the information state device which is coupled to that particular location. In this arrangement, the number of p information state devices is less than the number n of timing state devices. Less large-size latches are therefore needed. The invention also finds use in the resetting of a control module in processor after a trap by providing a timing silo which keeps track of the number of addresses which have been generated within the trap shadow.