Patents by Inventor Walter A. Carr
Walter A. Carr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11145418Abstract: A method of calculating blast injury metrics in a weapon training/IED blast scene can include: reconstructing topological layout of the scene having at least one real subject and a blast source; obtaining anthropometric and posture data for each real subject; obtaining anatomical soldier model for each real subject; identifying real position of at least one real pressure sensor on each soldier during a blast; positioning a virtual sensor on each anatomical soldier model to correspond with real pressure sensor on the real subject; calculating weapon signature of the blast source, the weapon signature including pressure versus time for a blast from the blast source; generating simulated pressure traces on each anatomical soldier model at east virtual pressure sensor; calculating blast injury metrics for the at least one real subject; and generating a report that includes the blast injury metrics for the at least one real subject.Type: GrantFiled: November 26, 2019Date of Patent: October 12, 2021Assignees: CFD RESEARCH CORPORATION, The Government of The United States, as represented by the Secretary of the ArmyInventors: Andrzej Przekwas, Harsha T. Garimella, Timothy Zehnbauer, Zhijian Chen, Vincent Harrand, Raj Kumar Gupta, Gary Kamimori, Walter Carr
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Publication number: 20200303081Abstract: A method of calculating blast injury metrics in a weapon training/IED blast scene can include: reconstructing topological layout of the scene having at least one real subject and a blast source; obtaining anthropometric and posture data for each real subject; obtaining anatomical soldier model for each real subject; identifying real position of at least one real pressure sensor on each soldier during a blast; positioning a virtual sensor on each anatomical soldier model to correspond with real pressure sensor on the real subject; calculating weapon signature of the blast source, the weapon signature including pressure versus time for a blast from the blast source; generating simulated pressure traces on each anatomical soldier model at east virtual pressure sensor; calculating blast injury metrics for the at least one real subject; and generating a report that includes the blast injury metrics for the at least one real subject.Type: ApplicationFiled: November 26, 2019Publication date: September 24, 2020Inventors: Andrzej Przekwas, Harsha T. Garimella, Timothy Zehnbauer, Zhijian Chen, Vincent Harrand, Raj Kumar Gupta, Gary Kamimori, Walter Carr
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Patent number: 9418093Abstract: A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.Type: GrantFiled: September 12, 2011Date of Patent: August 16, 2016Assignee: Altera CorporationInventors: Paul Nadj, David Walter Carr, Edward D. Funnekotter
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Publication number: 20140181126Abstract: A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.Type: ApplicationFiled: September 12, 2011Publication date: June 26, 2014Applicant: Altera CorporationInventors: Paul Nadj, David Walter Carr, Edward D. Funnekotter
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Patent number: 8086641Abstract: An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a search path of the search tree for the applied search key. The search engine device is also configured to read a bitmap associated with the leaf node to identify a pointer to associated data for the longest prefix match. The pointer has a value that is based on a position of a set bit within the bitmap that corresponds to a set bit within the span prefix mask that signifies the longest prefix match.Type: GrantFiled: December 17, 2008Date of Patent: December 27, 2011Assignee: NetLogic Microsystems, Inc.Inventor: David Walter Carr
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Patent number: 8032561Abstract: A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.Type: GrantFiled: August 16, 2001Date of Patent: October 4, 2011Assignee: Altera CorporationInventors: Paul Nadj, David Walter Carr, Edward D. Funnekotter
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Patent number: 7953721Abstract: Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).Type: GrantFiled: December 21, 2007Date of Patent: May 31, 2011Assignee: NetLogic Microsystems, Inc.Inventors: Gary Depelteau, David Walter Carr
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Patent number: 7825777Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n?1, . . . , 0]) and a second n-bit operand (e.g., B[n?1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( ā¦ ? ( ( C i ? ( A 0 + B 0 _ ) + A 0 ? B 0 _ ) ? ( A 1 + B 1 _ ) + A 1 ? B 1 _ ) ? ā¦ ? ( A n - 2 + B n - 2 _ ) + A n - 2 ? B n - 2 _ ) ? ( A n - 1 + B n - 1 _ ) + A n - 1 ? B n - 1 _ , ānā is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.Type: GrantFiled: March 30, 2006Date of Patent: November 2, 2010Assignee: Integrated Device Technology, Inc.Inventors: Tingjun Wen, David Walter Carr, Tadeusz Kwasniewski
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Patent number: 7792812Abstract: A search engine device that supports a Patricia trie arrangement of search keys includes an array of comparator cells that supports parallel decoding of the Patricia trie. This array of comparator cells processes a plurality of distinguishing bit identifiers for nodes in the Patricia trie in parallel with a corresponding plurality of bits of an applied search key during a search operation. In response to this processing, the array generates a match signal that identifies a location of a matching search key candidate within the Patricia trie.Type: GrantFiled: March 31, 2006Date of Patent: September 7, 2010Assignee: NetLogic Microsystems, Inc.Inventor: David Walter Carr
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Patent number: 7747599Abstract: A search engine device includes a hierarchical memory that is configured to store a b-tree of search prefixes and span prefix masks (SPMs). These SPMs are evaluated during each search operation to identify search prefixes that match an applied search key yet reside at nodes of the b-tree that are not traversed during the search operation. The search engine device also includes handle memory. This handle memory is configured to support a respective handle memory block for each search prefix within each of a plurality of nodes of the b-tree that reside at a leaf parent level within the b-tree. Each of these handle memory blocks may have sufficient capacity to support one result handle per bit within a span prefix mask associated with a corresponding search prefix. In other cases, each of these handle memory blocks may have sufficient capacity to support only M+1 handles, where M is a positive integer corresponding to a quantity of search prefixes supported by each of a plurality of leaf nodes within the b-tree.Type: GrantFiled: July 19, 2005Date of Patent: June 29, 2010Assignee: NetLogic Microsystems, Inc.Inventors: Gary Michael Depelteau, David Walter Carr
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Patent number: 7739460Abstract: An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.Type: GrantFiled: September 26, 2007Date of Patent: June 15, 2010Assignee: Integrated Device Technology, Inc.Inventor: David Walter Carr
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Patent number: 7200793Abstract: Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.Type: GrantFiled: March 22, 2002Date of Patent: April 3, 2007Assignee: Altera CorporationInventors: Subramani Kengeri, David Walter Carr, Paul Nadj, Jaya Prakash Samala
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Publication number: 20040081165Abstract: Apparatus and method for shaping ATM cell traffic emitted onto a virtual path connection in an ATM network are described. Component virtual channel connections are arbitrated at an aggregation point utilizing an arbitration technique. The technique provides both virtual path shaping and controllability of underlying virtual channel connections with an improved fairness performance amongst all the aggregating virtual channel connections.Type: ApplicationFiled: September 10, 2003Publication date: April 29, 2004Applicant: Alcatel Canada Inc.Inventors: David Walter Carr, Denny L.S. Lee, Tom Davis
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Patent number: 6643293Abstract: Apparatus and method for shaping ATM cell traffic emitted onto a virtual path connection in an ATM network are described. Component virtual channel connections are arbitrated at an aggregation point utilizing an arbitration technique. The technique provides both virtual path shaping and controllability of underlying virtual channel connections with an improved fairness performance amongst all the aggregating virtual channel connections.Type: GrantFiled: November 27, 1998Date of Patent: November 4, 2003Assignee: Alcatel Canada Inc.Inventors: David Walter Carr, Denny L. S. Lee
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Patent number: 6163542Abstract: An apparatus and a method for shaping ATM cell traffic emitted onto a virtual path connection in an ATM network are described. Component virtual channel connections are arbitrated at an aggregation point utilizing a hierarchical, multi-level arbitration technique. The technique provides both virtual path shaping and controllability of underlying virtual channel connections with an improved fairness performance amongst all the aggregating virtual channel connections.Type: GrantFiled: September 5, 1997Date of Patent: December 19, 2000Inventors: David Walter Carr, Denny L. S. Lee
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Patent number: 5375277Abstract: A personal extraction cart for supporting and restraining a person to facilitate movement of that person from an extrication point, wherein the cart includes a frame having a support surface. The support surface has upper and lower faces and a leg support portion and a back support portion defining a longitudinal length with oppositely disposed longitudinal edges. The leg and back support portions have a use position in which the upper faces of each of those portions are angled relative to each other along the longitudinal length of the frame. Wheels are preferably attached below the support surface for facilitating movement of the cart in its transportation position.Type: GrantFiled: August 11, 1993Date of Patent: December 27, 1994Assignee: Ferno-Washington, Inc.Inventors: Walter Carr, Jerry L. Taylor
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Patent number: H448Abstract: A process for preparing an energetic mixture of 1,2,4-butanetroil trinitr and nitroglycerin by forming a polyol mixture of 1,2,4-butanetriol and glycerin, and then nitrating the polyol mixture with a mixture of nitric and sulfuric acids.Type: GrantFiled: July 6, 1987Date of Patent: March 1, 1988Assignee: The United States of America as represented by the Secretary of the NavyInventors: Robert E. Farncomb, Walter A. Carr