Abstract: Prior to transmission, data bits are arranged into matrices having blocks sized in accordance with a size or rate of an error burst. The matrices are arranged into an ordered set having first and second dimensions. One or more sets of check bits are generated for each block of data bits. At least one set of first check bits relates to the first dimension, and at least one set of second check bits relates to said second dimension. The ordered set of matrices is transmitted across a transmission channel and received at a decoder-corrector. One or more errors in data bits of the ordered set of matrices are detected and corrected, by the decoder-corrector, based on the check bits.

Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.

Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.

Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.

Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.

Abstract: A data transmission system for use in a mass memory system includes a unique EDAC which corrects all single component errors and detects all double component errors. High speed operation permits use of the EDAC on address and control lines as well as on data lines. In memory systems which use virtual memory addressing, further efficiency and economy is achieved by incorporating a partial implementation of the EDAC encoding in the same virtual memory address translation unit in which virtual memory address are calculated. False indications of error are avoided by ANDing the signals which indicate the location of an error, with an inclusive OR of all the bits which indicate the existence of an error but not the location of the error. In such manner, the error location signals are set to zero when the error detection bits indicate that there are no errors.

Abstract: A fault-tolerating memory system has a data memory with a large number (M+N) of data storage words each having a length greater than the length of user data to be stored in that word; the extra word length is used for at least an error-detecting-and-correcting (EDAC) code. The user data is stored in a smaller number (N) of the words, with the remaining number (M) of words being used to store a map of which portions, if any, of each word are not usable. The N words of user data storage can include S normal storage words and (N-S) spare words, each for use if one of the normal storage words has too many unusable portions. A portion of each word length can contain at least one spare word portion, to which a block of data can be moved if any bit of a like-sized portion of the normal storage word is unusable.

Abstract: A rectangular antenna array includes a plurality of systolic vertical line arrays. Each vertical line array includes a plurality of signal processors. Within each line array, the signals received at any one moment are held or delayed as required, and the processors progressively form partial sums in an upward direction during first clock intervals and in a downward direction during alternate clock intervals. During each clock intervals, complete sums for one sample interval appear at an end of the vertical line array. The sums appear alternately at the top and the bottom of the line arrays. Beamforming in the horizontal direction is accomplished with systolic horizontal adders coupled to the tops and bottoms of the vertical line arrays. The horizontal adders transfer information and add in one direction during first clock intervals, and then in the other direction during third clock intervals of a four-interval cycle.