Patents by Inventor Walter Braddock

Walter Braddock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070138506
    Abstract: A self-aligned enhancement mode or depletion mode nitride based metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that in comprised of gallium oxides or indium oxides compounds (30) positioned immediately on top of the nitride compound semiconductor structure, and a second insulating layer comprised of either (a) oxygen and rare earth elements, (b) gallium oxygen and rare earth elements, or (c) gallium+indium and rare earth elements positioned immediately on top of said first layer. Together the lower indium oxide or gallium oxide layer and the second insulating layer form a epitaxial oxide gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14) that is based on the nitride family of compound semiconductors.
    Type: Application
    Filed: November 17, 2004
    Publication date: June 21, 2007
    Inventor: Walter Braddock
  • Publication number: 20060076630
    Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.
    Type: Application
    Filed: February 9, 2005
    Publication date: April 13, 2006
    Inventor: Walter Braddock