Abstract: A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.

Abstract: A low voltage submicron CMOS circuit (10) for providing an output bandgap voltage (V.sub.BG) that is substantially independent of temperature and power supply variations has been provided. The CMOS circuit utilizes parasitic transistors (28-30) to create a delta voltage that has a positive temperature coefficient across a differential pair of NMOS transistors (14, 16). This delta voltage is then converted into differential currents which are amplified and mirrored and summed together to provide an output current (I.sub.O) that has a positive temperature coefficient. This output current is then passed through a series network including a resistor element (52) and a parasitic PNP junction transistor (31) to provide a bandgap voltage of 1.2 volts wherein the voltage across the resistor element has a positive temperature coefficient and the voltage across the parasitic PNP junction transistor has an inherent negative temperature coefficient.

Abstract: A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.

Abstract: A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage.

Abstract: A source terminated transmission line driver circuit having an output coupled to a transmission line through a resistor is provided. The driver circuit has a gate circuit for providing first and second signals and a pulse generator circuit responsive to the second signal of the gate circuit for providing a pulse current at an output when the second signal is switching from a first logic state to a second logic state and for otherwise providing a quiescent current at the output. The driver circuit also has a first circuit responsive to the first output signal of the gate circuit for sourcing current to the output of the source terminated transmission line driver circuit, the first circuit being responsive to the second output signal of the gate circuit for sinking an adjustable current at the output of the source terminated transmission line driver circuit.

Abstract: A BiMOS voltage reference circuit which includes a bandgap circuit for providing a predetermined voltage at an output of the circuit that is independent of temperature. A start-up and bias circuit coupled to the bandgap circuit for providing a start-up current to the bandgap circuit during power-up and for providing a bias current to the bandgap circuit after power-up. A feedback circuit coupled to the bandgap circuit for maintaining the bias current to the bandgap circuit independent of power supply variations wherein the predetermined voltage at the output of the circuit is also independent of power supply variations as well as temperature.

Abstract: A circuit is provided that generates a predetermined regulated voltage between first and second terminals that is positioned between first and second power supply voltage rails wherein the predetermined regulated voltage is substantially independent of temperature and power supply variation. The circuit includes a bandgap circuit for providing a predetermined reference potential that is substantially independent of temperature and power supply variation. A resistive circuit provides first and second voltages which are referenced with respect to the first supply voltage rail. A level translator circuit translates the second voltage provided by the resistive circuit to a third voltage which is referenced with respect to the second supply voltage rail.

Abstract: An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

Abstract: A BICMOS driver circuit is provided having high input impedence and high output current drive with low static power dissipation that provides supply voltages and full logic output voltage swing for circuits having submicron dimensions. An inverter circuit is coupled to a voltage divider circuit and the input terminal for inverting the input signal. A complementary emitter follower circuit is coupled to an output terminal for providing a digital output signal. A current source circuit is coupled to the complementary emitter follower circuit and the input terminal for sourcing current to the complementary emitter follower circuit in response to the input signal. A bipolar bias circuit is coupled to the complementary emitter follower circuit and the inverter circuit for biasing the complementary emitter follower circuit in response to an inverted input signal.

Abstract: A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.

Abstract: A BIMOS memory cell is formed by providing a CMOS static RAM cell with an additional NPN bipolar transistor to provide additional drive current during the read cycle to improve the read time of the memory cell.

Abstract: A circuit is described that provides a quick charge and discharge of a row of memory cells. A first transistor has its collector-emitter path coupled between a first voltage and a row of memory cells, and a base coupled to an input terminal. A second transistor has its collector-emitter path coupled to the first voltage by a resistor and to a voltage level setting device, and a base coupled to the input terminal. A third transistor has its collector-emitter path coupled between the row of memory cells and a second voltage, and a base coupled to a voltage level shifting device. As the row of memory cells are selected, the third transistor becomes less conductive, thereby sinking less current from the row of memory cells and allowing the inherent capacitance of the row of memory cells to charge more quickly. As the row of memory cells are deselected, the third transistor becomes more conductive, thereby sinking more current from the row of memory cells and discharging the inherent capacitance more quickly.

Abstract: A transient driver circuit for use with a logic circuit having an emitter-follower output stage that sources current to a load connected to an output thereof in response to an applied logic signal being at a first logic level. The transient driver circuit includes a first NPN transistor the collector-emitter path of which is coupled between the output of the logic circuit and the negative power supply rail, a second NPN transistor having its collector-emitter path couple between a positive power supply rail and the collector of the first NPN transistor and its base adapted to receive the logic signal and feedback circuitry that is responsive to a rise in the collector voltage of the second NPN transistor occurring as the logic signal switches to a second logic level for supplying current drive to the base of the first NPN transistor thereby turning it on to sink a large transient current at the output of the logic circuit.

Abstract: A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.

Abstract: A voltage level translator circuit is provided that translates an input voltage referenced to an ECL supply voltage V.sub.CC to a voltage referenced to a TTL supply voltage V.sub.EE independent of power supply voltage variations. A first and a second embodiment have reference circuits coupled to receive a data input signal for providing a single signal referenced to a first supply voltage terminal to a current mirror. An output circuit is coupled to the current mirror for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled to receive a data input signal for referencing a voltage on a first supply voltage terminal to a voltage on a second supply voltage terminal. A voltage setting circuit is coupled to the reference circuit for setting a voltage within the reference circuit.

Abstract: Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P type plug is used to connect the P collector of the PNP to the P base of the NPN in a region where the P base and P collector overlap. A single N epi-region serves as the base of the PNP and the collector of the NPN. The P plug is located within this N epi-region but part of the N epi-region adjacent to or around the P plug is left so that internal connection of the PNP base and NPN collector is not cut off by the P plug. The structure is particularly suited for use in large memory arrays. The method of fabrication is also described.

Abstract: An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.

Abstract: A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.

Abstract: A majority logic gate is comprised of a plurality of depletion mode switching devices and includes Schottky diodes for both level shifting and clamping the high logic level output voltage to ground. A plurality of MESFET input devices each have their gate electrode coupled to one input of the majority logic gate. Each MESFET input device has a source coupled to ground and a drain coupled to a current load device. The voltage level at the drain at each of the input devices changes from a logical "0" to a logical "1" state depending upon the number of inputs which are at a logical "1" level. The drain voltage is then level shifted down. The high logic level output voltage is clamped to ground by means of two Schottky diodes the first of which has a cathode coupled to ground and an anode coupled to the anode of the second diode, the cathode of the second diode being coupled to the output of the circuit.

Abstract: A temperature sensor circuit is disclosed which employs a plurality of semiconductor junctions arranged either in a current-mirror configuration or a bridge configuration in order to provide a differential output voltage which is linearly proportional to temperature. The temperature sensor circuit is ideally suited for fabrication as an integrated circuit, and the differential output voltage is relatively insensitive to integrated circuit processing variations as well as power supply variations. By providing a differential output signal, the circuit is particularly useful in high noise environments such as automotive applications.