Patents by Inventor Walter D. Eisenhower

Walter D. Eisenhower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4212100
    Abstract: An N-channel MOS integrated circuit device having a composite metal gate structure which has improved temperature stability. The gate structure uses a polysilicon layer to separate the conventional metal gate from the conventional underlying gate oxide. The metal gate and the polysilicon layer extend laterally at least to the lateral extent of the gate region. This composite metal gate structure improves the temperature stability of the IC, and may be used, for example, in read-only memory (ROM) applications. The polysilicon layer is formed without additional photolithographic steps.
    Type: Grant
    Filed: September 23, 1977
    Date of Patent: July 15, 1980
    Assignee: MOS Technology, Inc.
    Inventors: John Paivinen, Walter D. Eisenhower, Jr., Ernest R. Helfrich
  • Patent number: 4074301
    Abstract: The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide.
    Type: Grant
    Filed: November 1, 1976
    Date of Patent: February 14, 1978
    Assignee: MOS Technology, Inc.
    Inventors: John O. Paivinen, Walter D. Eisenhower
  • Patent number: 4011105
    Abstract: The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide.
    Type: Grant
    Filed: September 15, 1975
    Date of Patent: March 8, 1977
    Assignee: MOS Technology, Inc.
    Inventors: John O. Paivinen, Walter D. Eisenhower