Abstract: A transistor for detecting gases in the ambient air. The transistor includes a plurality of electrodes with one electrode being a gate electrode. At least one electrode is individually coated by a ceramic. An ionogel connects all electrodes with each other, the ionogel being an ionic liquid immobilized by a matrix. The use of such a transistor as an air-quality sensor is described. A process for making the transistor is also described. The process includes providing a plurality of electrodes, wherein one of the electrodes is a gate electrode; individually depositing a ceramic precursor on at least one of the plurality of electrodes; and connecting the plurality of electrodes with an ionogel, the ionogel being an ionic liquid immobilized by a matrix. A transistor produced by the process is also described.

Abstract: A pressure sensor has a substrate and a transistor structure. The substrate has a cavity formed in the substrate. The transistor structure is arranged above the cavity. The transistor structure has a flexible heterostructure and at least one source contact, drain contact, and gate contact each connected to the heterostructure in an electrically conductive manner. The heterostructure is configured to assume a position corresponding to a pressure ratio between a first pressure in the cavity and a second pressure on a side of the heterostructure opposite the cavity. The transistor structure is configured to provide an electrical signal corresponding to the position.

Abstract: A method for producing an electronic circuit device includes a step of providing a substrate and a step of processing a III-V-connection semiconductor circuit on a substrate top side of the substrate. The III-V-connection semiconductor circuit has at least one III-V-connection semiconductor component, a second III-V-connection semiconductor component, and an electrical conductor, which electrically conductively connects the first III-V connection semiconductor component and the second III-V connection semiconductor component. In an arranging step, a metal layer or a metallized interconnect device is arranged on a rear side of the substrate, opposite the substrate top side, as an electrical contact surface for refeeding a current for a power electronic circuit.

Abstract: A commutation cell having at least one electrical capacitor, at least one controllable semiconductor switch and at least one semiconductor which is connected in series with the controllable semiconductor switch. The commutation cell has three circuit substrates situated in parallel with one another. The controllable semiconductor switch is connected in series with the semiconductor via a circuit substrate situated partially between the controllable semiconductor switch and the semiconductor, and the two remaining circuit substrates being connected to one another in an electrically conductive manner via a subassembly made up of the controllable semiconductor switch, the semiconductor and the circuit substrate situated partially between the controllable semiconductor switch and the semiconductor, the electrical capacitor being switched between the two remaining circuit substrates, separately from the subassembly.

Abstract: A pressure sensor has a substrate and a transistor structure. The substrate has a cavity formed in the substrate. The transistor structure is arranged above the cavity. The transistor structure has a flexible heterostructure and at least one source contact, drain contact, and gate contact each connected to the heterostructure in an electrically conductive manner. The heterostructure is configured to assume a position corresponding to a pressure ratio between a first pressure in the cavity and a second pressure on a side of the heterostructure opposite the cavity. The transistor structure is configured to provide an electrical signal corresponding to the position.

Abstract: A commutation cell having at least one electrical capacitor, at least one controllable semiconductor switch and at least one semiconductor which is connected in series with the controllable semiconductor switch. The commutation cell has three circuit substrates situated in parallel with one another. The controllable semiconductor switch is connected in series with the semiconductor via a circuit substrate situated partially between the controllable semiconductor switch and the semiconductor, and the two remaining circuit substrates being connected to one another in an electrically conductive manner via a subassembly made up of the controllable semiconductor switch, the semiconductor and the circuit substrate situated partially between the controllable semiconductor switch and the semiconductor, the electrical capacitor being switched between the two remaining circuit substrates, separately from the subassembly.

Abstract: A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches. Each fin includes a GaN/AlGaN heterolayer region formed on the side wall and including a channel region extending essentially parallel to the side wall. Each fin includes a gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in the associated trench on the side wall. A common source terminal region arranged above the fins is connected to a first end of the channel region in a vicinity of the upper sides. A common drain terminal region arranged above the back side is connected to a second end of the channel region in a vicinity of the front side.

Abstract: A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches. Each fin includes a GaN/AlGaN heterolayer region formed on the side wall and including a channel region extending essentially parallel to the side wall. Each fin includes a gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in the associated trench on the side wall. A common source terminal region arranged above the fins is connected to a first end of the channel region in a vicinity of the upper sides. A common drain terminal region arranged above the back side is connected to a second end of the channel region in a vicinity of the front side.