Abstract: A filament, heat shield, supporting base comprised of SiC with ceramic insulators and top plate that together form an effusion assembly for use in the vacuum evaporation, molecular beam epitaxy, and ultra high vacuum deposition of epitaxial materials. The effusion assembly used together with a crucible and source material allow for the vacuum evaporation of species above 1250° C. when quantities of reactive gaseous species such as oxygen, sulphur, or reactive nitrogen are present in the deposition chamber. The relative chemical inertness of SiC even at elevated temperatures allows the SiC filament assembly to be used at high temperature especially in the presence of oxygen for the high purity epitaxial nucleation and growth layered electronic materials including semiconductors, metals, oxides, dielectric multilayer stacks, sulfides and oxides.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor sure from the second insulating oxide layer. A refractory mal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first conductive oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.

Abstract: A self-aligned enhancement mode metal-sulfide-oxide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide-oxide gate insulating structure. The gallium sulfide-oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5×10−10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

Abstract: A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: A preseparation processor for use in capillary electrophoresis is described. The preseparation processor contains sample processing material, preferably in the form of a membrane, for use in concentrating or chemically processing a sample, or catalyzing a chemical reaction. It is particularly suited to the concentration of dilute samples or the purification of contaminated samples. The preseparation processor facilitates reliable and reproducible separation of analytes by eliminating inconsistencies caused by a reversal of the electroosmotic flow otherwise induced by the sample processing material.