Abstract: Circuitry for detecting nonstandard video signals is disclosed. This circuitry is used in a sampled data video signal processing system to control signal processing steps which utilize a frame store memory. The detecting circuitry includes a programmable counter which generates a standard horizontal pulse signal having a 70 ns pulse width by counting down a sampling clock signal that has a frequency proportional to the color subcarrier frequency of the video signals. The circuitry generates another horizontal pulse signal having a pulse width of less than 140 ns from the horizontal sync pulses of the input video signals. These pulse signals are compared in a coincidence detector which produces a signal that is in a first state when the pulses of the two signals overlap at least once in every twenty-five horizontal line times and in a second state otherwise.

Abstract: A flat-field television image having reduced visibility of horizontal scan lines is generated by receiving first and second fields of interlaced video and progressively generating a scanned image within a time for one incoming field. The progressive scanned image is formed from "real" and interpolated lines of luminance. In this arrangement the interpolated line is formed by weighting samples from time-successive lines. To improve the vertical detail of a progressively scanned image vertical detail information which may be obtained from the chrominance channel is combined with both "real" and interpolated lines, or one to the exclusion of the other, to enhance the image displayed.

Abstract: In a video signal processor for a progressive scanning system, an interlaced composite video signal, repeating at an f.sub.H line rate of approximately 16 KHz, is coupled to a comb filter. Separated luminance and chrominance signals are developed at respective output terminals of the comb filter. The chrominance signal is demodulated to develop color mixture signals. The luminance and color mixture signals are applied to a color matrix for generating a first set of R, G, B color signals, with each signal repeating at the f.sub.H line rate. A time compression circuit is coupled to the output of the color matrix for time compressing the R, G, B color signals to generate a comparable set of three time compressed and processed color signals, with each time compressed signal repeating at a double line rate of 2f.sub.H. The video signal processor is also capable of converting f.sub.H line rate, interlaced R, G, B signals, obtained from an external video source, into double line rate, non-interlaced signals.

Abstract: An electrical signal processing network includes a high order, two port, three terminal filter, and means coupled to the filter for synthesizing, at a single terminal, an impedance exhibiting the transfer function of the filter. The synthesized impedance can be coupled to a single point in a signal path for filtering signals in accordance with the transfer function of the filter.

Abstract: A flat-field television image having reduced visibility of horizontal scan lines is generated by receiving first and second fields of interlaced video and progressively generating a scanned image within a time for one incoming field. The progressive scanned image is formed from "real" and interpolated lines of luminance. In this arrangement the interpolated line is formed by weighting samples from time-successive lines. To improve the vertical detail of a progressively scanned image vertical detail information which may be obtained from the chrominance channel is combined with both "real" and interpolated lines, or one to the exclusion of the other, to enhance the image displayed.

Abstract: A flat-field television image having reduced visibility of horizontal scan lines is generated by receiving first and second fields of interlaced video and progressively generating a scanned image within a time period for one incoming field. The progressively scanned image is formed from "real" and interpolated lines of luminance. In this arrangement a speed-up processor is provided for generating the high speed output. The speed-up processor incorporates an input sequence device, a storage device and an output sequence device. In the implementation the input sequence device rearranges the original data stream such that samples from the input data stream are stored in the rearranged sequence. The output sequence means selects the samples from the storage device such that the output samples are restored to their original sequence and provided at the faster rate.

Abstract: A signal to be delayed is applied to a frequency selective path including an inverting active bandpass filter and to a non-frequency selective path including a voltage-to-current converter. The paths are coupled to a signal combiner which produces an output current having a first component proportional to the output current of the converter and a second component directly proportional to the filter output voltage and inversely proportional to the value of a gain control resistor. The resistor is selected to provide a predetermined ratio of the output current components to provide an overall allpass characteristic for the delay circuit and biased to conduct no current under quiescent signal conditions thereby reducing power dissipation. Several circuits may be cascaded for such purposes as peaking and delay equalization in television receivers, video disc players or the like.

Abstract: Frequency multiplier includes common-emitter input amplifying stage receiving fundamental frequency input signals at input transistor base. Output amplifying stage has output transistor with its base linked to input transistor collector, and with its collector coupled to narrow band load circuit tuned to a selected harmonic frequency. Emitter circuit of output transistor includes parallel resonant circuit tuned to input signal fundamental frequency. Non-linear negative feedback path between output transistor emitter and input transistor base includes capacitor in series with paralleled, oppositely poled diodes.