Abstract: The invention relates to a device for detecting and displaying movements, whereby the device comprises a housing and position detection means, which are placed on the housing and provided for detecting the current position data of a reference point of the device. The inventive device also comprises data processing means for processing position data detected by the position detection means, and comprises a display device, which is provided on the housing while serving to display an image consisting of detected and processed position data.

Abstract: A telecommunication terminal is provided which includes a recording device for recording acoustic user information, a memory for storing acoustic effect data, and a mixing device which is embodied in such a way that, in a mixing mode of operation, the acoustic user information recorded by the recording device is modified using the acoustic effect data stored in the memory. The telecommunication terminal also includes a control device which is connected to the mixing device and automatically ends the mixing mode after a predetermined operating mode.

Abstract: The invention relates to a device for detecting and displaying movements, whereby the device comprises a housing and position detection means, which are placed on the housing and provided for detecting the current position data of a reference point of the device. The inventive device also comprises data processing means for processing position data detected by the position detection means, and comprises a display device, which is provided on the housing while serving to display an image consisting of detected and processed position data.

Abstract: A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY).

Abstract: A method and apparatus for operating a multiprocessor control computer provides that at least one part of the central processors may be connected through switches to each half of a duplicated central bus system and through switches to each half of duplicated memory banks of a common memory. With the duplication and selectable switching, the multiprocessor control computer may be normally operated while the remainder of the computer may be connected to a special computer for modification of the normal operating program. Data already in one memory bank can also be stored in another memory bank under the same address so that after the special operating time of both memory banks, the memory banks contain the same information at the same addresses. Two specific processors are provided for operating and security functions, while the remainder of the processors carry out exchange functions.

Abstract: A multiprocessor central control unit a switching system with a main memory (CMY) including, aside from a tolerable timing slip, synchronously parallel operated memory block pairs (MB3a/MB3b) during normal operation. The main memory (CMY), together with the central processors (BP, CP . . . IOC . . . ), is connected to a central bus system (B:CMY0/CMY1). The data stored in parallel in the memory blocks of the memory block pairs (e.g., MB3a/MB3b) are EDC-protected. The processors have access to the memory block pairs (e.g. MB3a/MB3b). Upon the occurrence of a multiple error in an indicated second memory block (e.g., MB3b) of a memory block pair (MB3a/MB3b), the second memory block (MB3b) is isolated from the bus system (B:CMY0/B:CMY1) via an automatic memory configuration.