Patents by Inventor Walter Fabian

Walter Fabian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5310104
    Abstract: The invention discloses a novel method and apparatus for cleaving semiconductor wafers into individual die which comprises mounting the wafer upon an adherent resilient air impermeable membrane while the latter is flat. Cleaving is achieved by using air pressure to inflate the membrane to cause bending and tensile stresses on the wafer brought about by its adhesion to the inflating membrane. These stresses cleave the wafer along the scribe marks to form individual die. The die may be easily removed by the application of a vacuum to the underside of the membrane which draws it against a perforated undulatory grid dimensioned according to the die dimensions to reduce the surface contact. This reduces adhesion of the die to the membrane to facilitate a low stress pick-off of the die.
    Type: Grant
    Filed: December 16, 1991
    Date of Patent: May 10, 1994
    Assignee: General Electric Company
    Inventors: Simon A. Zaidel, Walter Fabian, Brian G. Baxter, Albert J. Manoni
  • Patent number: 4525919
    Abstract: A method for forming a field effect transistor having a submicron gate length. A gate electrode is formed by angularly depositing metal through an aperture formed in a thick masking layer. A substrate upon which the gate electrode is to be formed is placed in an apparatus for depositing a stream of evaporated metal through the aperture onto portions of the substrate surface exposed by the aperture. The stream is directed at a selective oblique angle .theta. with respect to a normal to the surface of such substrate. Portions of the exposed surface of the substrate are shadowed from the obliquely directed stream of evaporated metal by an edge of the aperture formed in the thick masking layer. Thus, only selected portions of such obliquely directed stream of evaporated metal are deposited onto unshadowed portions of the substrate to thereby provide the gate electrode.
    Type: Grant
    Filed: June 16, 1982
    Date of Patent: July 2, 1985
    Assignee: Raytheon Company
    Inventor: Walter Fabian
  • Patent number: 4499656
    Abstract: A method of fabricating gallium arsenide devices in which contact isolation is provided by a deep mesa step structure. Step coverage of deposited conductive films is facilitated by preferential orientation of the non-centrosymmetric crystal substrate and wet anisotropic etching that provides a sloped step. Problems of fine line definition of the Schottky anode contact in the photolithographic process are addressed by a two-step exposure of a single layer of thick photoresist followed by a chlorobenzene soak prior to development that ensures a retrograde resist profile needed for good lift-off of undesired evaporated metal. Mesas as deep as 7 .mu.m have been obtained, which permit the fabrication of monolithic planar mixer millimeter-wave diodes with low series resistance and reduced parasitic capacitance.
    Type: Grant
    Filed: August 15, 1983
    Date of Patent: February 19, 1985
    Assignee: Sperry Corporation
    Inventors: Walter Fabian, Frank H. Spooner