Abstract: The portion which exceeds a given level, of a charge signal present at a radiation sensor, is passed to a storage site via the conduction path beneath a gate electrode. The remainder of the charge signal is removed to a drain through the same conduction path, the radiation sensor being reset to a reference level in the process. The use of a common conduction path for setting both the charge signal "skimming" level and the reset level, improves the uniformity of the skimming process from one sensor to another.

Abstract: The first potential well of a charge-coupled device (CCD) register is initially filled from a source diffusion and then the effective depth of this well is reduced and the excess charge removed. The depth reduction and charge removal may be concurrently accomplished by changing the relative potential between the source diffusion and the electrode or electrodes producing the first potential well in a sense to cause this diffusion to operate as a drain for the excess charge. The charge remaining in the first potential well is relatively noise free, that is, it is at a predictable and reproducible level.

Abstract: The columns in known frame transfer type charge coupled device (CCD) image sensing arrays generally are spaced, center-to-center, a distance equal to the length of a stage in the C register. In the present array the center-to-center spacing of the columns is considerably reduced to obtain improved resolution in the row direction. The spacing is only 1/n'th of the length of each such C register stage, where n is the number of phases employed to operate the C register. The array is read out to the C register via a special electrode structure, 1/n'th of a row at a time, and the C register is read out in such a way that the row is reconstructed while being read from the C register. The special electrode structure temporarily stores a row of information and permits the 1/n'th of the row to be removed at a time. It also provides a potential barrier to isolate the C register during the time the C register is being read out.

Abstract: Output gate electrode structure between the storage matrix and the output register of a serial-parallel-serial (SPS) charge coupled device (CCD) memory. To permit high channel packing density in the matrix, the output register can have as few as M/N stages, where M is the number of channels in the matrix and N the number of phases employed for operating the register. The gate structure transfers 1/N'th of a word at a time to the output register and while this 1/N'th of a word is being propagated out of the register, the remaining part (or parts), if any, of the word are stored while the gate structure provides a potential barrier between this stored charge and the register.

Abstract: Charges initially are stored in each half I.sub.a and I.sub.b of each stage of a charge coupled device (CCD) array. A first field is obtained from the charges stored during a first time period by combining the charges in the halves I.sub.a and I.sub.b of each stage. A second field which may be interlaced with the first is obtained from the charges stored during a second time period by combining the charge in the I.sub.b half of each stage with the charge in the I.sub.a half of the following stage. The combining of charges may be performed within the photosensing array to obtain vertical interlacing and within the system output register to obtain horizontal interlacing.