Abstract: A method of synthesizing a circuit employs a technology parameter extraction circuit which is synthesized with constraints and simulated to derive values of performance parameters, and then, based on the derived values, a predetermined high-level circuit description of a second circuit is modified and then synthesized using the same constraints. Optional steps include the creation and substitution of a sub-circuit model to permit correct simulation, or substitution of an alternative sub-circuit to synthesize a second circuit that cannot otherwise be synthesized directly.

Abstract: A triggerable bipolar flip-flop, such as an I.sup.2 L flip-flop, is comprised of a master stage, a slave stage, two logically-controlled current sources, and a clock-controlled current sink. The current source and current sink are coupled to the set and reset inputs of the master stage. When the clock signal is at one level, the current sink draws current from the set and reset inputs of the master stage, thereby disabling the master stage. When the clock signal is at a second level, the current sink turns off permitting the current source to enable the master stage. Logic signals control the current sources to selectively transmit current to the set or reset input of the master stage. Toggle, J-K, D, and pseudo D embodiments of the flip-flop may be provided.