Abstract: Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Abstract: The Internet is used to test an integrated circuit chip that is provided with boundary scan circuitry and plugged into a circuit board at a customer's location. A host computer at the manufacturer's location runs a web page server having the ability to remotely test a customer's chip. The process is initiated by the customer connecting the circuit board to his own computer and logging onto the web site. The customer transmits customer identification and other data to the web server, which then transmits a downloader program and a JAVA program script to the customer's computer. The customer's computer then uses the downloader program to transmit high and low level device data describing the functionality of the chip to the host computer, which then generates and transmits a set of suitable test vectors to the customer's computer.