Abstract: A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information.

Abstract: A system for providing power to peripheral components associated with a personal computer is disclosed. A local power management unit is located at each controller for a peripheral component in order to provide a distributive power management arrangement. The local power management units communicate with an activity monitor provided in a central power management unit. The foregoing arrangement permits power to be maintained to the bus interface microchips at all times. Deactuation of a controller associated with a peripheral component is accomplished through inhibiting the clock signal produced by the local power management unit associated with the controller. By maintaining power to the bus interface microchips, power leakage through the bus interface microchips is eliminated.

Abstract: A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This is accomplished by providing first and second alternate RAM sets of 12 registers each, which are accessed in the same 768K to 960K space as the standard twelve registers located in the 768K to 960K space. Access to the 24 registers in the first and second alternate sets of registers is controlled by two control bits. These bits translate address signals directed to the 768K to 960K space to be directed to one or the other of the first and second alternate sets of 12 registers; so that the alternate registers are accessed in the same space as the standard 12 registers in this 768K to 960K space.

Abstract: A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.

Abstract: A computer system includes a bus and a plurality of devices coupled to the bus. A CPU within the bus controller generates addresses for data transfers to and from the devices. A bus controller generates control signals for the data transfers. A data transfer rate controlled by the control signals is varied so that the data transfer rate is optimal for data transfers to and from each device. The data transfer rate for a data transfer to or from a first device is based on a subset of address bits used by the CPU to address the first device.