Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. A memory array cell comprises a pair of cross-coupled inverters forming a first latch for storing data. The first latch has an output connected to a read bit line. True and complement write word and bit line input to the first latch. A first set of pass gates connects between the true and complement write word and bit line inputs via gates and the input of said first latch. The first set of pass gates is responsive to a first clock via a second pass gate. A pair of cross-coupled inverters forms a second latch of a Level Sensitive Scan Design (LSSD).

Abstract: Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range.

Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.

Abstract: A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

Abstract: Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level.

Abstract: A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.