Patents by Inventor Walter Heinrich Lipponer

Walter Heinrich Lipponer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address
    Patent number: 5768294
    Abstract: An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Memory implemented error detection and correction code using memory modules
    Patent number: 5761221
    Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Klaus Ruediger Baat, Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Memory implemented error detection and correction code with address parity bits
    Patent number: 5751745
    Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: May 12, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Memory implemented error detection and correction code with address parity bits
    Patent number: 5691996
    Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: November 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen