Patents by Inventor Walter J Dauksher

Walter J Dauksher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9355966
    Abstract: A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: May 31, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adam Gallegos, Walter J. Dauksher
  • Publication number: 20150008571
    Abstract: A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.
    Type: Application
    Filed: July 8, 2013
    Publication date: January 8, 2015
    Inventors: Adam Gallegos, Walter J. Dauksher
  • Publication number: 20130105063
    Abstract: A method for fabricating a laminate structure includes providing a laminate core, forming at least one laminate layer on each opposing side of the laminate core, the laminate core and the at least one laminate layer on each opposing side of the laminate core forming a laminate structure, determining an out-of-plane displacement for the laminate structure at a temperature of interest, the out-of-plane displacement corresponding to warpage, and if the warpage exceeds a predetermined value, modifying at least one of the laminate layers to reduce the warpage.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 2, 2013
    Inventors: Walter J. Dauksher, Adam Gallegos
  • Patent number: 7659622
    Abstract: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: February 9, 2010
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Walter J. Dauksher, Dennis H. Eaton
  • Patent number: 6661666
    Abstract: A device having features for enhancing the cooling of an electronic package subject to laminar air flow. The features include a bluff body, located adjacent the electronic package and within the laminar air flow, for creating turbulence in the air flow to enhance the cooling of the package. The turbulence creates a greater cooling effect of the air flow on the electronic package, and the bluff body can include a rod or other structure mounted adjacent the electronic package. The bluff body can also be mounted on the electronic package or on a heat sink mounted on top of the package.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: December 9, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Walter J. Dauksher
  • Patent number: 6320754
    Abstract: A device that reduces the interfacial stress caused by differential thermal expansion in an IC/PC board assembly can be created by attaching an annular part, that has a higher coefficient of thermal expansion, to the IC at an elevated temperature. When the assembly cools the annular part contracts and compresses the IC, increasing the change in size of the IC and reducing the stress in the IC/PC joint.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: November 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Walter J Dauksher, Pedro F Engel