Patents by Inventor Walter J. Downey

Walter J. Downey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140280408
    Abstract: Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Walter J. Downey
  • Patent number: 7227341
    Abstract: A circuit for use with a power supply coupled in a switched leg of, for example, a lighting circuit, is described. The circuit provides a low impedance near the zero crossing of the AC signal and a high impedance thereafter, thereby allowing the power supply to draw current that bypasses, for instance, a light bulb.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: June 5, 2007
    Assignee: Echelon Corporation
    Inventors: Walter J. Downey, Jacques H. Wilson, II
  • Patent number: 6636117
    Abstract: An improvement in a buffer for driving a signal onto a power line is described. The buffer includes a second order filter. With the improvement, the collector-to-emitter potential of an emitter follower is maintained constant to substantially reduce the distortion associated with base-collector capacitance.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: October 21, 2003
    Assignee: Echelon Corporation
    Inventors: Philip H. Sutterlin, Walter J. Downey
  • Publication number: 20030122625
    Abstract: An improvement in a buffer for driving a signal onto a power line is described. The buffer includes a second order filter. With the improvement, the collector-to-emitter potential of an emitter follower is maintained constant to substantially reduce the distortion associated with base-collector capacitance.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: Philip H. Sutterlin, Walter J. Downey
  • Patent number: 6484018
    Abstract: A method and apparatus for defining and generating a digital waveform such as used for the local oscillator for a down converter in a receiver is disclosed. The method and apparatus is particularly useful where the digital waveform is not an integer submultiple of a reference signal. A plurality of different digital waveforms meeting the timing criteria but having different combinations of segments needed to meet the timing criteria are generated. Each of the digital waveforms so generated are tested in, for instance, a receiver to enable the selection of the best combination of segments.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: November 19, 2002
    Assignee: Echleon Corporation
    Inventors: Walter J. Downey, Mark Adrian Stubbs, Luna Chen, Philip H. Sutterlin
  • Patent number: 6442381
    Abstract: A method and apparatus for defining and generating a digital waveform such as used for the local oscillator for a down converter in a receiver is disclosed. The method and apparatus is particularly useful where the digital waveform is not an integer submultiple of a reference signal. A plurality of different digital waveforms meeting the timing criteria but having different combinations of segments needed to meet the timing criteria are generated. Each of the digital waveforms so generated are tested in, for instance, a receiver to enable the selection of the best combination of segments.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: August 27, 2002
    Assignee: Echelon Corporation
    Inventors: Walter J. Downey, Mark Adrian Stubbs, Luna Chen, Philip H. Sutterlin
  • Patent number: 6414968
    Abstract: A dual channel transceiver which operates at two different frequencies and which may be used in a network using older transceivers operating at a single frequency is disclosed. A pilot tone is transmitted by the transceiver when it is using the second channel to cause the older transfers to remain synchronized and thereby prevent them from transmitting data which would otherwise interfere with the data on the second channel. The relative magnitude of the signals on both channels is compared to prevent the detection of cross-talk on the second channel as data.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: July 2, 2002
    Assignee: Echelon Corporation
    Inventors: Philip H. Sutterlin, Walter J. Downey, Mark Adrian Stubbs, Luna Chen
  • Patent number: 6295625
    Abstract: A “hint” signal is developed which points to suspected erroneous bits in received data by examining anomalies in the signal. More particularly, a delta phase pointer which quantifies one of the anomalies is used. The realigning of an IQ pointer provides an additional anomaly which is prioritized along with the delta phase pointer. The particular error correcting code used for the power line application provides seven check bits for a data byte and permits the correction of up to two errors. A third error is correctable through use of the hint signal and a parity bit.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: September 25, 2001
    Assignee: Echelon Corporation
    Inventors: Walter J. Downey, Mark A. Stubbs, Philip H. Sutterlin, Luna Chen
  • Patent number: 6043635
    Abstract: A power supply for operating from a switched leg of an AC power line is described. A switch provides current during the beginning of each AC half cycle to an inductor and charges a capacitor. When the switch is open, the inductor continues to charge the capacitor. During the time that the inductor is coupled to that AC line, the switched leg is open. For instance, the signal used to close the switch also prevents a triac in the switched leg from conducting.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: March 28, 2000
    Assignee: Echelon Corporation
    Inventor: Walter J. Downey
  • Patent number: 5828676
    Abstract: A robust encoding and decoding system of the present invention for communicating binary information using angular modulation system is disclosed. Binary information to be transmitted is data words consisting of 8 data bits, a parity bit, and two additional coding bits at the end of the data word. A transmitter transmits the data words using a binary phase-shift keying (BPSK) modulated signal. The receiver compares the phase of incoming BPSK modulated signal against a local reference signal and records the phase characteristics of the BPSK signal. The receiver also records the amplitude of the recovered data signal. The receiver demodulates and decodes the BPSK signal using a rotating frame of reference that tracks the current phase of the recovered data signal. The receiver tests the parity bit of each word to detect errors. If an error is detected, the receiver attempts to correct the error using the record phase and amplitude information.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: October 27, 1998
    Assignee: Echelon Corporation
    Inventors: Amy O. Hurlbut, Philip H. Sutterlin, Walter J. Downey
  • Patent number: 5701240
    Abstract: A power supply for operating from a switched leg of an AC power line and for powering a transmitter is described. A switch provides current during the beginning of each AC half cycle to an inductor and charges a capacitor. When the switch is open, the inductor continues to charge the capacitor. During the time that the inductor is coupled to that AC line, the switched leg is open. For instance, the signal used to close the switch also prevents a triac in the switched leg from conducting. When the voltage on the capacitor drops to a predetermined level transmission from the transmitter is inhibited. A timing circuit is used to determine when to begin transmissions to compensate for variables in the node such as line voltages and part tolerances.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: December 23, 1997
    Assignee: Echelon Corporation
    Inventors: Walter J. Downey, Philip H. Sutterlin, J. Marcus Stewart, Amy O. Hurlbut
  • Patent number: 5553081
    Abstract: In a communications system, an apparatus and method for detecting a valid signal from noise. An adaptive threshold is used to qualify a received signal. The adaptive threshold is set according to the number of false detects occurring within a given time interval. The number of false detects is initially determined by a quick qualification process. This initial number is subsequently adjusted by a more accurate qualification process. The transmitted signal is modulated with a particular pattern. Upon receiving the signal, it is demodulated to retrieve that pattern. The demodulated pattern is correlated against multiple reference patterns and combined to provide a measure of peak correlation that is independent of pattern phase. Furthermore, a tone detector is used to distinguish valid signals from interfering tones. Two different types of detection methods are performed in parallel. One is based on the energy of the received signal, whereas the other is based on the correlation of the received signal.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: September 3, 1996
    Assignee: Echelon Corporation
    Inventors: Walter J. Downey, Philip H. Sutterlin, Amy O. Hurlbut, J. Marcus Stewart, Benjamin W. Chui, Robert A. Dolin, Jr.
  • Patent number: 5471209
    Abstract: A sigma-delta A/D converter having a digital logic gate core. The converter is comprised of a loop filter for shaping the converter's quantization noise spectrum. The loop filter is comprised of an unbuffered CMOS logic gate inverter which can be implemented by a gate array. A quantizer is coupled to the loop filter. A logic gate buffer is configured as a one-bit comparator, which is used to perform the quantization. This logic gate buffer can be one of the gates of a gate array. A sampler is coupled to the quantizer for sampling the quantized signal. This sampler can also be implemented by digital circuitry of a gate array. The signal from the sampler is fed into a decimator. The decimator outputs a digital signal representative of the amplitude of the analog signal.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: November 28, 1995
    Assignee: Echelon Corporation
    Inventors: Philip H. Sutterlin, Walter J. Downey
  • Patent number: 5463662
    Abstract: An apparatus for snubbing or blanking digital signals representing a band of signals that includes an encoded carrier signal transmitted over a power line. An average signal level is compared with the instantaneous signal level to develop a blanking circuit control signal. Additionally, snubbing occurs in the circuit which determines the average signal level to prevent noise from building-up the average signal level. A hold-off signal is used in this circuit to prevent the average signal level from being latched permanently low. A unique infinite impulse filter subtracts out the D.C. offset thereby improving the dynamic range of the blanking. Additionally, the average signal level is used by AGC logic to control the gain at the front end of the apparatus. The state and switching of the AGC is controlled to minimize errors.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: October 31, 1995
    Assignee: Echelon Corporation
    Inventors: Philip H. Sutterlin, Walter J. Downey, Benjamin W. Chui, J. Marcus Stewart, Amy O. Hurlbut
  • Patent number: 5239686
    Abstract: An RF transceiver achieves a fast switching time between transmit and receive modes by leaving the transmit oscillator on all the time. The transmit chain comprises a wide pulling voltage controlled crystal oscillator that operates at one third the transmit frequency followed by a frequency tripler/filter/amplifier chain that can be quickly switched on and off. By operating the transmit oscillator at one third the transmit frequency, only the third harmonic of the oscillator falls into the sensitive receive frequency band. Further isolation during the receive mode is achieved by gating off the frequency tripler, pulling the frequency of the oscillator out of the receive band, electronically detuning the harmonic filter and switching off the transmitter's power amplifier.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: August 24, 1993
    Assignee: Echelon Corporation
    Inventor: Walter J. Downey
  • Patent number: 5206657
    Abstract: A radio frequency antenna comprises a pair of double-sided printed circuit boards that are etched on each side to form conductive loops around the periphery of each board. The circuit boards are spaced apart by standoffs and the loops are electrically coupled in series. An impedance matching network is incorporated on one of the circuit boards.
    Type: Grant
    Filed: October 7, 1991
    Date of Patent: April 27, 1993
    Assignee: Echelon Corporation
    Inventor: Walter J. Downey